1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (c) 2019 MediaTek Inc. 4*4882a593Smuzhiyun * Author: Yong Liang <yong.liang@mediatek.com> 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #ifndef _DT_BINDINGS_RESET_CONTROLLER_MT2712 8*4882a593Smuzhiyun #define _DT_BINDINGS_RESET_CONTROLLER_MT2712 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #define MT2712_TOPRGU_INFRA_SW_RST 0 11*4882a593Smuzhiyun #define MT2712_TOPRGU_MM_SW_RST 1 12*4882a593Smuzhiyun #define MT2712_TOPRGU_MFG_SW_RST 2 13*4882a593Smuzhiyun #define MT2712_TOPRGU_VENC_SW_RST 3 14*4882a593Smuzhiyun #define MT2712_TOPRGU_VDEC_SW_RST 4 15*4882a593Smuzhiyun #define MT2712_TOPRGU_IMG_SW_RST 5 16*4882a593Smuzhiyun #define MT2712_TOPRGU_INFRA_AO_SW_RST 8 17*4882a593Smuzhiyun #define MT2712_TOPRGU_USB_SW_RST 9 18*4882a593Smuzhiyun #define MT2712_TOPRGU_APMIXED_SW_RST 10 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun #define MT2712_TOPRGU_SW_RST_NUM 11 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun #endif /* _DT_BINDINGS_RESET_CONTROLLER_MT2712 */ 23