1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (C) 2018 Xilinx, Inc. 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun #ifndef _DT_BINDINGS_ZYNQMP_POWER_H 7*4882a593Smuzhiyun #define _DT_BINDINGS_ZYNQMP_POWER_H 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #define PD_USB_0 22 10*4882a593Smuzhiyun #define PD_USB_1 23 11*4882a593Smuzhiyun #define PD_TTC_0 24 12*4882a593Smuzhiyun #define PD_TTC_1 25 13*4882a593Smuzhiyun #define PD_TTC_2 26 14*4882a593Smuzhiyun #define PD_TTC_3 27 15*4882a593Smuzhiyun #define PD_SATA 28 16*4882a593Smuzhiyun #define PD_ETH_0 29 17*4882a593Smuzhiyun #define PD_ETH_1 30 18*4882a593Smuzhiyun #define PD_ETH_2 31 19*4882a593Smuzhiyun #define PD_ETH_3 32 20*4882a593Smuzhiyun #define PD_UART_0 33 21*4882a593Smuzhiyun #define PD_UART_1 34 22*4882a593Smuzhiyun #define PD_SPI_0 35 23*4882a593Smuzhiyun #define PD_SPI_1 36 24*4882a593Smuzhiyun #define PD_I2C_0 37 25*4882a593Smuzhiyun #define PD_I2C_1 38 26*4882a593Smuzhiyun #define PD_SD_0 39 27*4882a593Smuzhiyun #define PD_SD_1 40 28*4882a593Smuzhiyun #define PD_DP 41 29*4882a593Smuzhiyun #define PD_GDMA 42 30*4882a593Smuzhiyun #define PD_ADMA 43 31*4882a593Smuzhiyun #define PD_NAND 44 32*4882a593Smuzhiyun #define PD_QSPI 45 33*4882a593Smuzhiyun #define PD_GPIO 46 34*4882a593Smuzhiyun #define PD_CAN_0 47 35*4882a593Smuzhiyun #define PD_CAN_1 48 36*4882a593Smuzhiyun #define PD_GPU 58 37*4882a593Smuzhiyun #define PD_PCIE 59 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun #endif 40