1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. */ 3*4882a593Smuzhiyun 4*4882a593Smuzhiyun #ifndef __ABI_MACH_T194_POWERGATE_T194_H_ 5*4882a593Smuzhiyun #define __ABI_MACH_T194_POWERGATE_T194_H_ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #define TEGRA194_POWER_DOMAIN_AUD 1 8*4882a593Smuzhiyun #define TEGRA194_POWER_DOMAIN_DISP 2 9*4882a593Smuzhiyun #define TEGRA194_POWER_DOMAIN_DISPB 3 10*4882a593Smuzhiyun #define TEGRA194_POWER_DOMAIN_DISPC 4 11*4882a593Smuzhiyun #define TEGRA194_POWER_DOMAIN_ISPA 5 12*4882a593Smuzhiyun #define TEGRA194_POWER_DOMAIN_NVDECA 6 13*4882a593Smuzhiyun #define TEGRA194_POWER_DOMAIN_NVJPG 7 14*4882a593Smuzhiyun #define TEGRA194_POWER_DOMAIN_NVENCA 8 15*4882a593Smuzhiyun #define TEGRA194_POWER_DOMAIN_NVENCB 9 16*4882a593Smuzhiyun #define TEGRA194_POWER_DOMAIN_NVDECB 10 17*4882a593Smuzhiyun #define TEGRA194_POWER_DOMAIN_SAX 11 18*4882a593Smuzhiyun #define TEGRA194_POWER_DOMAIN_VE 12 19*4882a593Smuzhiyun #define TEGRA194_POWER_DOMAIN_VIC 13 20*4882a593Smuzhiyun #define TEGRA194_POWER_DOMAIN_XUSBA 14 21*4882a593Smuzhiyun #define TEGRA194_POWER_DOMAIN_XUSBB 15 22*4882a593Smuzhiyun #define TEGRA194_POWER_DOMAIN_XUSBC 16 23*4882a593Smuzhiyun #define TEGRA194_POWER_DOMAIN_PCIEX8A 17 24*4882a593Smuzhiyun #define TEGRA194_POWER_DOMAIN_PCIEX4A 18 25*4882a593Smuzhiyun #define TEGRA194_POWER_DOMAIN_PCIEX1A 19 26*4882a593Smuzhiyun #define TEGRA194_POWER_DOMAIN_PCIEX8B 21 27*4882a593Smuzhiyun #define TEGRA194_POWER_DOMAIN_PVAA 22 28*4882a593Smuzhiyun #define TEGRA194_POWER_DOMAIN_PVAB 23 29*4882a593Smuzhiyun #define TEGRA194_POWER_DOMAIN_DLAA 24 30*4882a593Smuzhiyun #define TEGRA194_POWER_DOMAIN_DLAB 25 31*4882a593Smuzhiyun #define TEGRA194_POWER_DOMAIN_CV 26 32*4882a593Smuzhiyun #define TEGRA194_POWER_DOMAIN_GPU 27 33*4882a593Smuzhiyun #define TEGRA194_POWER_DOMAIN_MAX 27 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun #endif 36