1*4882a593Smuzhiyun /* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ 2*4882a593Smuzhiyun #ifndef __DT_BINDINGS_POWER_RK3588_POWER_H__ 3*4882a593Smuzhiyun #define __DT_BINDINGS_POWER_RK3588_POWER_H__ 4*4882a593Smuzhiyun 5*4882a593Smuzhiyun /* VD_LITDSU */ 6*4882a593Smuzhiyun #define RK3588_PD_CPU_0 0 7*4882a593Smuzhiyun #define RK3588_PD_CPU_1 1 8*4882a593Smuzhiyun #define RK3588_PD_CPU_2 2 9*4882a593Smuzhiyun #define RK3588_PD_CPU_3 3 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun /* VD_BIGCORE0 */ 12*4882a593Smuzhiyun #define RK3588_PD_CPU_4 4 13*4882a593Smuzhiyun #define RK3588_PD_CPU_5 5 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun /* VD_BIGCORE1 */ 16*4882a593Smuzhiyun #define RK3588_PD_CPU_6 6 17*4882a593Smuzhiyun #define RK3588_PD_CPU_7 7 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun /* VD_NPU */ 20*4882a593Smuzhiyun #define RK3588_PD_NPU 8 21*4882a593Smuzhiyun #define RK3588_PD_NPUTOP 9 22*4882a593Smuzhiyun #define RK3588_PD_NPU1 10 23*4882a593Smuzhiyun #define RK3588_PD_NPU2 11 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun /* VD_GPU */ 26*4882a593Smuzhiyun #define RK3588_PD_GPU 12 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun /* VD_VCODEC */ 29*4882a593Smuzhiyun #define RK3588_PD_VCODEC 13 30*4882a593Smuzhiyun #define RK3588_PD_RKVDEC0 14 31*4882a593Smuzhiyun #define RK3588_PD_RKVDEC1 15 32*4882a593Smuzhiyun #define RK3588_PD_VENC0 16 33*4882a593Smuzhiyun #define RK3588_PD_VENC1 17 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun /* VD_DD01 */ 36*4882a593Smuzhiyun #define RK3588_PD_DDR01 18 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun /* VD_DD23 */ 39*4882a593Smuzhiyun #define RK3588_PD_DDR23 19 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun /* VD_LOGIC */ 42*4882a593Smuzhiyun #define RK3588_PD_CENTER 20 43*4882a593Smuzhiyun #define RK3588_PD_VDPU 21 44*4882a593Smuzhiyun #define RK3588_PD_RGA30 22 45*4882a593Smuzhiyun #define RK3588_PD_AV1 23 46*4882a593Smuzhiyun #define RK3588_PD_VOP 24 47*4882a593Smuzhiyun #define RK3588_PD_VO0 25 48*4882a593Smuzhiyun #define RK3588_PD_VO1 26 49*4882a593Smuzhiyun #define RK3588_PD_VI 27 50*4882a593Smuzhiyun #define RK3588_PD_ISP1 28 51*4882a593Smuzhiyun #define RK3588_PD_FEC 29 52*4882a593Smuzhiyun #define RK3588_PD_RGA31 30 53*4882a593Smuzhiyun #define RK3588_PD_USB 31 54*4882a593Smuzhiyun #define RK3588_PD_PHP 32 55*4882a593Smuzhiyun #define RK3588_PD_GMAC 33 56*4882a593Smuzhiyun #define RK3588_PD_PCIE 34 57*4882a593Smuzhiyun #define RK3588_PD_NVM 35 58*4882a593Smuzhiyun #define RK3588_PD_NVM0 36 59*4882a593Smuzhiyun #define RK3588_PD_SDIO 37 60*4882a593Smuzhiyun #define RK3588_PD_AUDIO 38 61*4882a593Smuzhiyun #define RK3588_PD_SECURE 39 62*4882a593Smuzhiyun #define RK3588_PD_SDMMC 40 63*4882a593Smuzhiyun #define RK3588_PD_CRYPTO 41 64*4882a593Smuzhiyun #define RK3588_PD_BUS 42 65*4882a593Smuzhiyun 66*4882a593Smuzhiyun /* VD_PMU */ 67*4882a593Smuzhiyun #define RK3588_PD_PMU1 43 68*4882a593Smuzhiyun 69*4882a593Smuzhiyun #endif 70