1*4882a593Smuzhiyun /* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ 2*4882a593Smuzhiyun #ifndef __DT_BINDINGS_POWER_RK3399_POWER_H__ 3*4882a593Smuzhiyun #define __DT_BINDINGS_POWER_RK3399_POWER_H__ 4*4882a593Smuzhiyun 5*4882a593Smuzhiyun /* VD_CORE_L */ 6*4882a593Smuzhiyun #define RK3399_PD_A53_L0 0 7*4882a593Smuzhiyun #define RK3399_PD_A53_L1 1 8*4882a593Smuzhiyun #define RK3399_PD_A53_L2 2 9*4882a593Smuzhiyun #define RK3399_PD_A53_L3 3 10*4882a593Smuzhiyun #define RK3399_PD_SCU_L 4 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun /* VD_CORE_B */ 13*4882a593Smuzhiyun #define RK3399_PD_A72_B0 5 14*4882a593Smuzhiyun #define RK3399_PD_A72_B1 6 15*4882a593Smuzhiyun #define RK3399_PD_SCU_B 7 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun /* VD_LOGIC */ 18*4882a593Smuzhiyun #define RK3399_PD_TCPD0 8 19*4882a593Smuzhiyun #define RK3399_PD_TCPD1 9 20*4882a593Smuzhiyun #define RK3399_PD_CCI 10 21*4882a593Smuzhiyun #define RK3399_PD_CCI0 11 22*4882a593Smuzhiyun #define RK3399_PD_CCI1 12 23*4882a593Smuzhiyun #define RK3399_PD_PERILP 13 24*4882a593Smuzhiyun #define RK3399_PD_PERIHP 14 25*4882a593Smuzhiyun #define RK3399_PD_VIO 15 26*4882a593Smuzhiyun #define RK3399_PD_VO 16 27*4882a593Smuzhiyun #define RK3399_PD_VOPB 17 28*4882a593Smuzhiyun #define RK3399_PD_VOPL 18 29*4882a593Smuzhiyun #define RK3399_PD_ISP0 19 30*4882a593Smuzhiyun #define RK3399_PD_ISP1 20 31*4882a593Smuzhiyun #define RK3399_PD_HDCP 21 32*4882a593Smuzhiyun #define RK3399_PD_GMAC 22 33*4882a593Smuzhiyun #define RK3399_PD_EMMC 23 34*4882a593Smuzhiyun #define RK3399_PD_USB3 24 35*4882a593Smuzhiyun #define RK3399_PD_EDP 25 36*4882a593Smuzhiyun #define RK3399_PD_GIC 26 37*4882a593Smuzhiyun #define RK3399_PD_SD 27 38*4882a593Smuzhiyun #define RK3399_PD_SDIOAUDIO 28 39*4882a593Smuzhiyun #define RK3399_PD_ALIVE 29 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun /* VD_CENTER */ 42*4882a593Smuzhiyun #define RK3399_PD_CENTER 30 43*4882a593Smuzhiyun #define RK3399_PD_VCODEC 31 44*4882a593Smuzhiyun #define RK3399_PD_VDU 32 45*4882a593Smuzhiyun #define RK3399_PD_RGA 33 46*4882a593Smuzhiyun #define RK3399_PD_IEP 34 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun /* VD_GPU */ 49*4882a593Smuzhiyun #define RK3399_PD_GPU 35 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun /* VD_PMU */ 52*4882a593Smuzhiyun #define RK3399_PD_PMU 36 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun #endif 55