1*4882a593Smuzhiyun /* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ 2*4882a593Smuzhiyun #ifndef __DT_BINDINGS_POWER_RK3368_POWER_H__ 3*4882a593Smuzhiyun #define __DT_BINDINGS_POWER_RK3368_POWER_H__ 4*4882a593Smuzhiyun 5*4882a593Smuzhiyun /* VD_CORE */ 6*4882a593Smuzhiyun #define RK3368_PD_A53_L0 0 7*4882a593Smuzhiyun #define RK3368_PD_A53_L1 1 8*4882a593Smuzhiyun #define RK3368_PD_A53_L2 2 9*4882a593Smuzhiyun #define RK3368_PD_A53_L3 3 10*4882a593Smuzhiyun #define RK3368_PD_SCU_L 4 11*4882a593Smuzhiyun #define RK3368_PD_A53_B0 5 12*4882a593Smuzhiyun #define RK3368_PD_A53_B1 6 13*4882a593Smuzhiyun #define RK3368_PD_A53_B2 7 14*4882a593Smuzhiyun #define RK3368_PD_A53_B3 8 15*4882a593Smuzhiyun #define RK3368_PD_SCU_B 9 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun /* VD_LOGIC */ 18*4882a593Smuzhiyun #define RK3368_PD_BUS 10 19*4882a593Smuzhiyun #define RK3368_PD_PERI 11 20*4882a593Smuzhiyun #define RK3368_PD_VIO 12 21*4882a593Smuzhiyun #define RK3368_PD_ALIVE 13 22*4882a593Smuzhiyun #define RK3368_PD_VIDEO 14 23*4882a593Smuzhiyun #define RK3368_PD_GPU_0 15 24*4882a593Smuzhiyun #define RK3368_PD_GPU_1 16 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun /* VD_PMU */ 27*4882a593Smuzhiyun #define RK3368_PD_PMU 17 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun #endif 30