1*4882a593Smuzhiyun /* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ 2*4882a593Smuzhiyun #ifndef __DT_BINDINGS_POWER_RK3366_POWER_H__ 3*4882a593Smuzhiyun #define __DT_BINDINGS_POWER_RK3366_POWER_H__ 4*4882a593Smuzhiyun 5*4882a593Smuzhiyun /* VD_CORE */ 6*4882a593Smuzhiyun #define RK3366_PD_A53_0 0 7*4882a593Smuzhiyun #define RK3366_PD_A53_1 1 8*4882a593Smuzhiyun #define RK3366_PD_A53_2 2 9*4882a593Smuzhiyun #define RK3366_PD_A53_3 3 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun /* VD_LOGIC */ 12*4882a593Smuzhiyun #define RK3366_PD_BUS 4 13*4882a593Smuzhiyun #define RK3366_PD_PERI 5 14*4882a593Smuzhiyun #define RK3366_PD_VIO 6 15*4882a593Smuzhiyun #define RK3366_PD_VIDEO 7 16*4882a593Smuzhiyun #define RK3366_PD_RKVDEC 8 17*4882a593Smuzhiyun #define RK3366_PD_WIFIBT 9 18*4882a593Smuzhiyun #define RK3366_PD_VPU 10 19*4882a593Smuzhiyun #define RK3366_PD_GPU 11 20*4882a593Smuzhiyun #define RK3366_PD_ALIVE 12 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun /* VD_PMU */ 23*4882a593Smuzhiyun #define RK3366_PD_PMU 13 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun #endif 26