1*4882a593Smuzhiyun /* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ 2*4882a593Smuzhiyun #ifndef __DT_BINDINGS_POWER_RK3288_POWER_H__ 3*4882a593Smuzhiyun #define __DT_BINDINGS_POWER_RK3288_POWER_H__ 4*4882a593Smuzhiyun 5*4882a593Smuzhiyun /** 6*4882a593Smuzhiyun * RK3288 Power Domain and Voltage Domain Summary. 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun /* VD_CORE */ 10*4882a593Smuzhiyun #define RK3288_PD_A17_0 0 11*4882a593Smuzhiyun #define RK3288_PD_A17_1 1 12*4882a593Smuzhiyun #define RK3288_PD_A17_2 2 13*4882a593Smuzhiyun #define RK3288_PD_A17_3 3 14*4882a593Smuzhiyun #define RK3288_PD_SCU 4 15*4882a593Smuzhiyun #define RK3288_PD_DEBUG 5 16*4882a593Smuzhiyun #define RK3288_PD_MEM 6 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun /* VD_LOGIC */ 19*4882a593Smuzhiyun #define RK3288_PD_BUS 7 20*4882a593Smuzhiyun #define RK3288_PD_PERI 8 21*4882a593Smuzhiyun #define RK3288_PD_VIO 9 22*4882a593Smuzhiyun #define RK3288_PD_ALIVE 10 23*4882a593Smuzhiyun #define RK3288_PD_HEVC 11 24*4882a593Smuzhiyun #define RK3288_PD_VIDEO 12 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun /* VD_GPU */ 27*4882a593Smuzhiyun #define RK3288_PD_GPU 13 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun /* VD_PMU */ 30*4882a593Smuzhiyun #define RK3288_PD_PMU 14 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun #endif 33