1*4882a593Smuzhiyun /* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ 2*4882a593Smuzhiyun #ifndef __DT_BINDINGS_POWER_RK3188_POWER_H__ 3*4882a593Smuzhiyun #define __DT_BINDINGS_POWER_RK3188_POWER_H__ 4*4882a593Smuzhiyun 5*4882a593Smuzhiyun /* VD_CORE */ 6*4882a593Smuzhiyun #define RK3188_PD_A9_0 0 7*4882a593Smuzhiyun #define RK3188_PD_A9_1 1 8*4882a593Smuzhiyun #define RK3188_PD_A9_2 2 9*4882a593Smuzhiyun #define RK3188_PD_A9_3 3 10*4882a593Smuzhiyun #define RK3188_PD_DBG 4 11*4882a593Smuzhiyun #define RK3188_PD_SCU 5 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun /* VD_LOGIC */ 14*4882a593Smuzhiyun #define RK3188_PD_VIDEO 6 15*4882a593Smuzhiyun #define RK3188_PD_VIO 7 16*4882a593Smuzhiyun #define RK3188_PD_GPU 8 17*4882a593Smuzhiyun #define RK3188_PD_PERI 9 18*4882a593Smuzhiyun #define RK3188_PD_CPU 10 19*4882a593Smuzhiyun #define RK3188_PD_ALIVE 11 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun /* VD_PMU */ 22*4882a593Smuzhiyun #define RK3188_PD_RTC 12 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun #endif 25