1*4882a593Smuzhiyun /* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ 2*4882a593Smuzhiyun #ifndef __DT_BINDINGS_POWER_RK3066_POWER_H__ 3*4882a593Smuzhiyun #define __DT_BINDINGS_POWER_RK3066_POWER_H__ 4*4882a593Smuzhiyun 5*4882a593Smuzhiyun /* VD_CORE */ 6*4882a593Smuzhiyun #define RK3066_PD_A9_0 0 7*4882a593Smuzhiyun #define RK3066_PD_A9_1 1 8*4882a593Smuzhiyun #define RK3066_PD_DBG 4 9*4882a593Smuzhiyun #define RK3066_PD_SCU 5 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun /* VD_LOGIC */ 12*4882a593Smuzhiyun #define RK3066_PD_VIDEO 6 13*4882a593Smuzhiyun #define RK3066_PD_VIO 7 14*4882a593Smuzhiyun #define RK3066_PD_GPU 8 15*4882a593Smuzhiyun #define RK3066_PD_PERI 9 16*4882a593Smuzhiyun #define RK3066_PD_CPU 10 17*4882a593Smuzhiyun #define RK3066_PD_ALIVE 11 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun /* VD_PMU */ 20*4882a593Smuzhiyun #define RK3066_PD_RTC 12 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun #endif 23