1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (C) 2017 Glider bvba 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun #ifndef __DT_BINDINGS_POWER_R8A77995_SYSC_H__ 6*4882a593Smuzhiyun #define __DT_BINDINGS_POWER_R8A77995_SYSC_H__ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun /* 9*4882a593Smuzhiyun * These power domain indices match the numbers of the interrupt bits 10*4882a593Smuzhiyun * representing the power areas in the various Interrupt Registers 11*4882a593Smuzhiyun * (e.g. SYSCISR, Interrupt Status Register) 12*4882a593Smuzhiyun */ 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun #define R8A77995_PD_CA53_CPU0 5 15*4882a593Smuzhiyun #define R8A77995_PD_CA53_SCU 21 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun /* Always-on power area */ 18*4882a593Smuzhiyun #define R8A77995_PD_ALWAYS_ON 32 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun #endif /* __DT_BINDINGS_POWER_R8A77995_SYSC_H__ */ 21