xref: /OK3568_Linux_fs/kernel/include/dt-bindings/power/r8a77980-sysc.h (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun  *
3*4882a593Smuzhiyun  * Copyright (C) 2018 Renesas Electronics Corp.
4*4882a593Smuzhiyun  * Copyright (C) 2018 Cogent Embedded, Inc.
5*4882a593Smuzhiyun  */
6*4882a593Smuzhiyun #ifndef __DT_BINDINGS_POWER_R8A77980_SYSC_H__
7*4882a593Smuzhiyun #define __DT_BINDINGS_POWER_R8A77980_SYSC_H__
8*4882a593Smuzhiyun 
9*4882a593Smuzhiyun /*
10*4882a593Smuzhiyun  * These power domain indices match the numbers of the interrupt bits
11*4882a593Smuzhiyun  * representing the power areas in the various Interrupt Registers
12*4882a593Smuzhiyun  * (e.g. SYSCISR, Interrupt Status Register)
13*4882a593Smuzhiyun  */
14*4882a593Smuzhiyun 
15*4882a593Smuzhiyun #define R8A77980_PD_A2SC2		0
16*4882a593Smuzhiyun #define R8A77980_PD_A2SC3		1
17*4882a593Smuzhiyun #define R8A77980_PD_A2SC4		2
18*4882a593Smuzhiyun #define R8A77980_PD_A2DP0		3
19*4882a593Smuzhiyun #define R8A77980_PD_A2DP1		4
20*4882a593Smuzhiyun #define R8A77980_PD_CA53_CPU0		5
21*4882a593Smuzhiyun #define R8A77980_PD_CA53_CPU1		6
22*4882a593Smuzhiyun #define R8A77980_PD_CA53_CPU2		7
23*4882a593Smuzhiyun #define R8A77980_PD_CA53_CPU3		8
24*4882a593Smuzhiyun #define R8A77980_PD_A2CN		10
25*4882a593Smuzhiyun #define R8A77980_PD_A3VIP0		11
26*4882a593Smuzhiyun #define R8A77980_PD_A2IR5		12
27*4882a593Smuzhiyun #define R8A77980_PD_CR7			13
28*4882a593Smuzhiyun #define R8A77980_PD_A2IR4		15
29*4882a593Smuzhiyun #define R8A77980_PD_CA53_SCU		21
30*4882a593Smuzhiyun #define R8A77980_PD_A2IR0		23
31*4882a593Smuzhiyun #define R8A77980_PD_A3IR		24
32*4882a593Smuzhiyun #define R8A77980_PD_A3VIP1		25
33*4882a593Smuzhiyun #define R8A77980_PD_A3VIP2		26
34*4882a593Smuzhiyun #define R8A77980_PD_A2IR1		27
35*4882a593Smuzhiyun #define R8A77980_PD_A2IR2		28
36*4882a593Smuzhiyun #define R8A77980_PD_A2IR3		29
37*4882a593Smuzhiyun #define R8A77980_PD_A2SC0		30
38*4882a593Smuzhiyun #define R8A77980_PD_A2SC1		31
39*4882a593Smuzhiyun 
40*4882a593Smuzhiyun /* Always-on power area */
41*4882a593Smuzhiyun #define R8A77980_PD_ALWAYS_ON		32
42*4882a593Smuzhiyun 
43*4882a593Smuzhiyun #endif /* __DT_BINDINGS_POWER_R8A77980_SYSC_H__ */
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