1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (C) 2018 Jacopo Mondi <jacopo+renesas@jmondi.org> 4*4882a593Smuzhiyun * Copyright (C) 2016 Glider bvba 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #ifndef __DT_BINDINGS_POWER_R8A77965_SYSC_H__ 8*4882a593Smuzhiyun #define __DT_BINDINGS_POWER_R8A77965_SYSC_H__ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun /* 11*4882a593Smuzhiyun * These power domain indices match the numbers of the interrupt bits 12*4882a593Smuzhiyun * representing the power areas in the various Interrupt Registers 13*4882a593Smuzhiyun * (e.g. SYSCISR, Interrupt Status Register) 14*4882a593Smuzhiyun */ 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun #define R8A77965_PD_CA57_CPU0 0 17*4882a593Smuzhiyun #define R8A77965_PD_CA57_CPU1 1 18*4882a593Smuzhiyun #define R8A77965_PD_A3VP 9 19*4882a593Smuzhiyun #define R8A77965_PD_CA57_SCU 12 20*4882a593Smuzhiyun #define R8A77965_PD_CR7 13 21*4882a593Smuzhiyun #define R8A77965_PD_A3VC 14 22*4882a593Smuzhiyun #define R8A77965_PD_3DG_A 17 23*4882a593Smuzhiyun #define R8A77965_PD_3DG_B 18 24*4882a593Smuzhiyun #define R8A77965_PD_A2VC1 26 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun /* Always-on power area */ 27*4882a593Smuzhiyun #define R8A77965_PD_ALWAYS_ON 32 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun #endif /* __DT_BINDINGS_POWER_R8A77965_SYSC_H__ */ 30