1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (C) 2016 Glider bvba 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun #ifndef __DT_BINDINGS_POWER_R8A7795_SYSC_H__ 6*4882a593Smuzhiyun #define __DT_BINDINGS_POWER_R8A7795_SYSC_H__ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun /* 9*4882a593Smuzhiyun * These power domain indices match the numbers of the interrupt bits 10*4882a593Smuzhiyun * representing the power areas in the various Interrupt Registers 11*4882a593Smuzhiyun * (e.g. SYSCISR, Interrupt Status Register) 12*4882a593Smuzhiyun */ 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun #define R8A7795_PD_CA57_CPU0 0 15*4882a593Smuzhiyun #define R8A7795_PD_CA57_CPU1 1 16*4882a593Smuzhiyun #define R8A7795_PD_CA57_CPU2 2 17*4882a593Smuzhiyun #define R8A7795_PD_CA57_CPU3 3 18*4882a593Smuzhiyun #define R8A7795_PD_CA53_CPU0 5 19*4882a593Smuzhiyun #define R8A7795_PD_CA53_CPU1 6 20*4882a593Smuzhiyun #define R8A7795_PD_CA53_CPU2 7 21*4882a593Smuzhiyun #define R8A7795_PD_CA53_CPU3 8 22*4882a593Smuzhiyun #define R8A7795_PD_A3VP 9 23*4882a593Smuzhiyun #define R8A7795_PD_CA57_SCU 12 24*4882a593Smuzhiyun #define R8A7795_PD_CR7 13 25*4882a593Smuzhiyun #define R8A7795_PD_A3VC 14 26*4882a593Smuzhiyun #define R8A7795_PD_3DG_A 17 27*4882a593Smuzhiyun #define R8A7795_PD_3DG_B 18 28*4882a593Smuzhiyun #define R8A7795_PD_3DG_C 19 29*4882a593Smuzhiyun #define R8A7795_PD_3DG_D 20 30*4882a593Smuzhiyun #define R8A7795_PD_CA53_SCU 21 31*4882a593Smuzhiyun #define R8A7795_PD_3DG_E 22 32*4882a593Smuzhiyun #define R8A7795_PD_A3IR 24 33*4882a593Smuzhiyun #define R8A7795_PD_A2VC0 25 /* ES1.x only */ 34*4882a593Smuzhiyun #define R8A7795_PD_A2VC1 26 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun /* Always-on power area */ 37*4882a593Smuzhiyun #define R8A7795_PD_ALWAYS_ON 32 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun #endif /* __DT_BINDINGS_POWER_R8A7795_SYSC_H__ */ 40