1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun #ifndef __DT_BINDINGS_POWER_PX30_POWER_H__ 3*4882a593Smuzhiyun #define __DT_BINDINGS_POWER_PX30_POWER_H__ 4*4882a593Smuzhiyun 5*4882a593Smuzhiyun /* VD_CORE */ 6*4882a593Smuzhiyun #define PX30_PD_A35_0 0 7*4882a593Smuzhiyun #define PX30_PD_A35_1 1 8*4882a593Smuzhiyun #define PX30_PD_A35_2 2 9*4882a593Smuzhiyun #define PX30_PD_A35_3 3 10*4882a593Smuzhiyun #define PX30_PD_SCU 4 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun /* VD_LOGIC */ 13*4882a593Smuzhiyun #define PX30_PD_USB 5 14*4882a593Smuzhiyun #define PX30_PD_DDR 6 15*4882a593Smuzhiyun #define PX30_PD_SDCARD 7 16*4882a593Smuzhiyun #define PX30_PD_CRYPTO 8 17*4882a593Smuzhiyun #define PX30_PD_GMAC 9 18*4882a593Smuzhiyun #define PX30_PD_MMC_NAND 10 19*4882a593Smuzhiyun #define PX30_PD_VPU 11 20*4882a593Smuzhiyun #define PX30_PD_VO 12 21*4882a593Smuzhiyun #define PX30_PD_VI 13 22*4882a593Smuzhiyun #define PX30_PD_GPU 14 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun /* VD_PMU */ 25*4882a593Smuzhiyun #define PX30_PD_PMU 15 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun #endif 28