1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Defines macros and constants for Renesas RZ/N1 pin controller pin 4*4882a593Smuzhiyun * muxing functions. 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun #ifndef __DT_BINDINGS_RZN1_PINCTRL_H 7*4882a593Smuzhiyun #define __DT_BINDINGS_RZN1_PINCTRL_H 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #define RZN1_PINMUX(_gpio, _func) \ 10*4882a593Smuzhiyun (((_func) << 8) | (_gpio)) 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun /* 13*4882a593Smuzhiyun * Given the different levels of muxing on the SoC, it was decided to 14*4882a593Smuzhiyun * 'linearize' them into one numerical space. So mux level 1, 2 and the MDIO 15*4882a593Smuzhiyun * muxes are all represented by one single value. 16*4882a593Smuzhiyun * 17*4882a593Smuzhiyun * You can derive the hardware value pretty easily too, as 18*4882a593Smuzhiyun * 0...9 are Level 1 19*4882a593Smuzhiyun * 10...71 are Level 2. The Level 2 mux will be set to this 20*4882a593Smuzhiyun * value - RZN1_FUNC_L2_OFFSET, and the Level 1 mux will be 21*4882a593Smuzhiyun * set accordingly. 22*4882a593Smuzhiyun * 72...103 are for the 2 MDIO muxes. 23*4882a593Smuzhiyun */ 24*4882a593Smuzhiyun #define RZN1_FUNC_HIGHZ 0 25*4882a593Smuzhiyun #define RZN1_FUNC_0L 1 26*4882a593Smuzhiyun #define RZN1_FUNC_CLK_ETH_MII_RGMII_RMII 2 27*4882a593Smuzhiyun #define RZN1_FUNC_CLK_ETH_NAND 3 28*4882a593Smuzhiyun #define RZN1_FUNC_QSPI 4 29*4882a593Smuzhiyun #define RZN1_FUNC_SDIO 5 30*4882a593Smuzhiyun #define RZN1_FUNC_LCD 6 31*4882a593Smuzhiyun #define RZN1_FUNC_LCD_E 7 32*4882a593Smuzhiyun #define RZN1_FUNC_MSEBIM 8 33*4882a593Smuzhiyun #define RZN1_FUNC_MSEBIS 9 34*4882a593Smuzhiyun #define RZN1_FUNC_L2_OFFSET 10 /* I'm Special */ 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun #define RZN1_FUNC_HIGHZ1 (RZN1_FUNC_L2_OFFSET + 0) 37*4882a593Smuzhiyun #define RZN1_FUNC_ETHERCAT (RZN1_FUNC_L2_OFFSET + 1) 38*4882a593Smuzhiyun #define RZN1_FUNC_SERCOS3 (RZN1_FUNC_L2_OFFSET + 2) 39*4882a593Smuzhiyun #define RZN1_FUNC_SDIO_E (RZN1_FUNC_L2_OFFSET + 3) 40*4882a593Smuzhiyun #define RZN1_FUNC_ETH_MDIO (RZN1_FUNC_L2_OFFSET + 4) 41*4882a593Smuzhiyun #define RZN1_FUNC_ETH_MDIO_E1 (RZN1_FUNC_L2_OFFSET + 5) 42*4882a593Smuzhiyun #define RZN1_FUNC_USB (RZN1_FUNC_L2_OFFSET + 6) 43*4882a593Smuzhiyun #define RZN1_FUNC_MSEBIM_E (RZN1_FUNC_L2_OFFSET + 7) 44*4882a593Smuzhiyun #define RZN1_FUNC_MSEBIS_E (RZN1_FUNC_L2_OFFSET + 8) 45*4882a593Smuzhiyun #define RZN1_FUNC_RSV (RZN1_FUNC_L2_OFFSET + 9) 46*4882a593Smuzhiyun #define RZN1_FUNC_RSV_E (RZN1_FUNC_L2_OFFSET + 10) 47*4882a593Smuzhiyun #define RZN1_FUNC_RSV_E1 (RZN1_FUNC_L2_OFFSET + 11) 48*4882a593Smuzhiyun #define RZN1_FUNC_UART0_I (RZN1_FUNC_L2_OFFSET + 12) 49*4882a593Smuzhiyun #define RZN1_FUNC_UART0_I_E (RZN1_FUNC_L2_OFFSET + 13) 50*4882a593Smuzhiyun #define RZN1_FUNC_UART1_I (RZN1_FUNC_L2_OFFSET + 14) 51*4882a593Smuzhiyun #define RZN1_FUNC_UART1_I_E (RZN1_FUNC_L2_OFFSET + 15) 52*4882a593Smuzhiyun #define RZN1_FUNC_UART2_I (RZN1_FUNC_L2_OFFSET + 16) 53*4882a593Smuzhiyun #define RZN1_FUNC_UART2_I_E (RZN1_FUNC_L2_OFFSET + 17) 54*4882a593Smuzhiyun #define RZN1_FUNC_UART0 (RZN1_FUNC_L2_OFFSET + 18) 55*4882a593Smuzhiyun #define RZN1_FUNC_UART0_E (RZN1_FUNC_L2_OFFSET + 19) 56*4882a593Smuzhiyun #define RZN1_FUNC_UART1 (RZN1_FUNC_L2_OFFSET + 20) 57*4882a593Smuzhiyun #define RZN1_FUNC_UART1_E (RZN1_FUNC_L2_OFFSET + 21) 58*4882a593Smuzhiyun #define RZN1_FUNC_UART2 (RZN1_FUNC_L2_OFFSET + 22) 59*4882a593Smuzhiyun #define RZN1_FUNC_UART2_E (RZN1_FUNC_L2_OFFSET + 23) 60*4882a593Smuzhiyun #define RZN1_FUNC_UART3 (RZN1_FUNC_L2_OFFSET + 24) 61*4882a593Smuzhiyun #define RZN1_FUNC_UART3_E (RZN1_FUNC_L2_OFFSET + 25) 62*4882a593Smuzhiyun #define RZN1_FUNC_UART4 (RZN1_FUNC_L2_OFFSET + 26) 63*4882a593Smuzhiyun #define RZN1_FUNC_UART4_E (RZN1_FUNC_L2_OFFSET + 27) 64*4882a593Smuzhiyun #define RZN1_FUNC_UART5 (RZN1_FUNC_L2_OFFSET + 28) 65*4882a593Smuzhiyun #define RZN1_FUNC_UART5_E (RZN1_FUNC_L2_OFFSET + 29) 66*4882a593Smuzhiyun #define RZN1_FUNC_UART6 (RZN1_FUNC_L2_OFFSET + 30) 67*4882a593Smuzhiyun #define RZN1_FUNC_UART6_E (RZN1_FUNC_L2_OFFSET + 31) 68*4882a593Smuzhiyun #define RZN1_FUNC_UART7 (RZN1_FUNC_L2_OFFSET + 32) 69*4882a593Smuzhiyun #define RZN1_FUNC_UART7_E (RZN1_FUNC_L2_OFFSET + 33) 70*4882a593Smuzhiyun #define RZN1_FUNC_SPI0_M (RZN1_FUNC_L2_OFFSET + 34) 71*4882a593Smuzhiyun #define RZN1_FUNC_SPI0_M_E (RZN1_FUNC_L2_OFFSET + 35) 72*4882a593Smuzhiyun #define RZN1_FUNC_SPI1_M (RZN1_FUNC_L2_OFFSET + 36) 73*4882a593Smuzhiyun #define RZN1_FUNC_SPI1_M_E (RZN1_FUNC_L2_OFFSET + 37) 74*4882a593Smuzhiyun #define RZN1_FUNC_SPI2_M (RZN1_FUNC_L2_OFFSET + 38) 75*4882a593Smuzhiyun #define RZN1_FUNC_SPI2_M_E (RZN1_FUNC_L2_OFFSET + 39) 76*4882a593Smuzhiyun #define RZN1_FUNC_SPI3_M (RZN1_FUNC_L2_OFFSET + 40) 77*4882a593Smuzhiyun #define RZN1_FUNC_SPI3_M_E (RZN1_FUNC_L2_OFFSET + 41) 78*4882a593Smuzhiyun #define RZN1_FUNC_SPI4_S (RZN1_FUNC_L2_OFFSET + 42) 79*4882a593Smuzhiyun #define RZN1_FUNC_SPI4_S_E (RZN1_FUNC_L2_OFFSET + 43) 80*4882a593Smuzhiyun #define RZN1_FUNC_SPI5_S (RZN1_FUNC_L2_OFFSET + 44) 81*4882a593Smuzhiyun #define RZN1_FUNC_SPI5_S_E (RZN1_FUNC_L2_OFFSET + 45) 82*4882a593Smuzhiyun #define RZN1_FUNC_SGPIO0_M (RZN1_FUNC_L2_OFFSET + 46) 83*4882a593Smuzhiyun #define RZN1_FUNC_SGPIO1_M (RZN1_FUNC_L2_OFFSET + 47) 84*4882a593Smuzhiyun #define RZN1_FUNC_GPIO (RZN1_FUNC_L2_OFFSET + 48) 85*4882a593Smuzhiyun #define RZN1_FUNC_CAN (RZN1_FUNC_L2_OFFSET + 49) 86*4882a593Smuzhiyun #define RZN1_FUNC_I2C (RZN1_FUNC_L2_OFFSET + 50) 87*4882a593Smuzhiyun #define RZN1_FUNC_SAFE (RZN1_FUNC_L2_OFFSET + 51) 88*4882a593Smuzhiyun #define RZN1_FUNC_PTO_PWM (RZN1_FUNC_L2_OFFSET + 52) 89*4882a593Smuzhiyun #define RZN1_FUNC_PTO_PWM1 (RZN1_FUNC_L2_OFFSET + 53) 90*4882a593Smuzhiyun #define RZN1_FUNC_PTO_PWM2 (RZN1_FUNC_L2_OFFSET + 54) 91*4882a593Smuzhiyun #define RZN1_FUNC_PTO_PWM3 (RZN1_FUNC_L2_OFFSET + 55) 92*4882a593Smuzhiyun #define RZN1_FUNC_PTO_PWM4 (RZN1_FUNC_L2_OFFSET + 56) 93*4882a593Smuzhiyun #define RZN1_FUNC_DELTA_SIGMA (RZN1_FUNC_L2_OFFSET + 57) 94*4882a593Smuzhiyun #define RZN1_FUNC_SGPIO2_M (RZN1_FUNC_L2_OFFSET + 58) 95*4882a593Smuzhiyun #define RZN1_FUNC_SGPIO3_M (RZN1_FUNC_L2_OFFSET + 59) 96*4882a593Smuzhiyun #define RZN1_FUNC_SGPIO4_S (RZN1_FUNC_L2_OFFSET + 60) 97*4882a593Smuzhiyun #define RZN1_FUNC_MAC_MTIP_SWITCH (RZN1_FUNC_L2_OFFSET + 61) 98*4882a593Smuzhiyun 99*4882a593Smuzhiyun #define RZN1_FUNC_MDIO_OFFSET (RZN1_FUNC_L2_OFFSET + 62) 100*4882a593Smuzhiyun 101*4882a593Smuzhiyun /* These are MDIO0 peripherals for the RZN1_FUNC_ETH_MDIO function */ 102*4882a593Smuzhiyun #define RZN1_FUNC_MDIO0_HIGHZ (RZN1_FUNC_MDIO_OFFSET + 0) 103*4882a593Smuzhiyun #define RZN1_FUNC_MDIO0_GMAC0 (RZN1_FUNC_MDIO_OFFSET + 1) 104*4882a593Smuzhiyun #define RZN1_FUNC_MDIO0_GMAC1 (RZN1_FUNC_MDIO_OFFSET + 2) 105*4882a593Smuzhiyun #define RZN1_FUNC_MDIO0_ECAT (RZN1_FUNC_MDIO_OFFSET + 3) 106*4882a593Smuzhiyun #define RZN1_FUNC_MDIO0_S3_MDIO0 (RZN1_FUNC_MDIO_OFFSET + 4) 107*4882a593Smuzhiyun #define RZN1_FUNC_MDIO0_S3_MDIO1 (RZN1_FUNC_MDIO_OFFSET + 5) 108*4882a593Smuzhiyun #define RZN1_FUNC_MDIO0_HWRTOS (RZN1_FUNC_MDIO_OFFSET + 6) 109*4882a593Smuzhiyun #define RZN1_FUNC_MDIO0_SWITCH (RZN1_FUNC_MDIO_OFFSET + 7) 110*4882a593Smuzhiyun /* These are MDIO0 peripherals for the RZN1_FUNC_ETH_MDIO_E1 function */ 111*4882a593Smuzhiyun #define RZN1_FUNC_MDIO0_E1_HIGHZ (RZN1_FUNC_MDIO_OFFSET + 8) 112*4882a593Smuzhiyun #define RZN1_FUNC_MDIO0_E1_GMAC0 (RZN1_FUNC_MDIO_OFFSET + 9) 113*4882a593Smuzhiyun #define RZN1_FUNC_MDIO0_E1_GMAC1 (RZN1_FUNC_MDIO_OFFSET + 10) 114*4882a593Smuzhiyun #define RZN1_FUNC_MDIO0_E1_ECAT (RZN1_FUNC_MDIO_OFFSET + 11) 115*4882a593Smuzhiyun #define RZN1_FUNC_MDIO0_E1_S3_MDIO0 (RZN1_FUNC_MDIO_OFFSET + 12) 116*4882a593Smuzhiyun #define RZN1_FUNC_MDIO0_E1_S3_MDIO1 (RZN1_FUNC_MDIO_OFFSET + 13) 117*4882a593Smuzhiyun #define RZN1_FUNC_MDIO0_E1_HWRTOS (RZN1_FUNC_MDIO_OFFSET + 14) 118*4882a593Smuzhiyun #define RZN1_FUNC_MDIO0_E1_SWITCH (RZN1_FUNC_MDIO_OFFSET + 15) 119*4882a593Smuzhiyun 120*4882a593Smuzhiyun /* These are MDIO1 peripherals for the RZN1_FUNC_ETH_MDIO function */ 121*4882a593Smuzhiyun #define RZN1_FUNC_MDIO1_HIGHZ (RZN1_FUNC_MDIO_OFFSET + 16) 122*4882a593Smuzhiyun #define RZN1_FUNC_MDIO1_GMAC0 (RZN1_FUNC_MDIO_OFFSET + 17) 123*4882a593Smuzhiyun #define RZN1_FUNC_MDIO1_GMAC1 (RZN1_FUNC_MDIO_OFFSET + 18) 124*4882a593Smuzhiyun #define RZN1_FUNC_MDIO1_ECAT (RZN1_FUNC_MDIO_OFFSET + 19) 125*4882a593Smuzhiyun #define RZN1_FUNC_MDIO1_S3_MDIO0 (RZN1_FUNC_MDIO_OFFSET + 20) 126*4882a593Smuzhiyun #define RZN1_FUNC_MDIO1_S3_MDIO1 (RZN1_FUNC_MDIO_OFFSET + 21) 127*4882a593Smuzhiyun #define RZN1_FUNC_MDIO1_HWRTOS (RZN1_FUNC_MDIO_OFFSET + 22) 128*4882a593Smuzhiyun #define RZN1_FUNC_MDIO1_SWITCH (RZN1_FUNC_MDIO_OFFSET + 23) 129*4882a593Smuzhiyun /* These are MDIO1 peripherals for the RZN1_FUNC_ETH_MDIO_E1 function */ 130*4882a593Smuzhiyun #define RZN1_FUNC_MDIO1_E1_HIGHZ (RZN1_FUNC_MDIO_OFFSET + 24) 131*4882a593Smuzhiyun #define RZN1_FUNC_MDIO1_E1_GMAC0 (RZN1_FUNC_MDIO_OFFSET + 25) 132*4882a593Smuzhiyun #define RZN1_FUNC_MDIO1_E1_GMAC1 (RZN1_FUNC_MDIO_OFFSET + 26) 133*4882a593Smuzhiyun #define RZN1_FUNC_MDIO1_E1_ECAT (RZN1_FUNC_MDIO_OFFSET + 27) 134*4882a593Smuzhiyun #define RZN1_FUNC_MDIO1_E1_S3_MDIO0 (RZN1_FUNC_MDIO_OFFSET + 28) 135*4882a593Smuzhiyun #define RZN1_FUNC_MDIO1_E1_S3_MDIO1 (RZN1_FUNC_MDIO_OFFSET + 29) 136*4882a593Smuzhiyun #define RZN1_FUNC_MDIO1_E1_HWRTOS (RZN1_FUNC_MDIO_OFFSET + 30) 137*4882a593Smuzhiyun #define RZN1_FUNC_MDIO1_E1_SWITCH (RZN1_FUNC_MDIO_OFFSET + 31) 138*4882a593Smuzhiyun 139*4882a593Smuzhiyun #define RZN1_FUNC_MAX (RZN1_FUNC_MDIO_OFFSET + 32) 140*4882a593Smuzhiyun 141*4882a593Smuzhiyun #endif /* __DT_BINDINGS_RZN1_PINCTRL_H */ 142