1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * This header provides constants for Tegra pinctrl bindings. 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved. 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * Author: Laxman Dewangan <ldewangan@nvidia.com> 8*4882a593Smuzhiyun */ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #ifndef _DT_BINDINGS_PINCTRL_TEGRA_H 11*4882a593Smuzhiyun #define _DT_BINDINGS_PINCTRL_TEGRA_H 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun /* 14*4882a593Smuzhiyun * Enable/disable for diffeent dt properties. This is applicable for 15*4882a593Smuzhiyun * properties nvidia,enable-input, nvidia,tristate, nvidia,open-drain, 16*4882a593Smuzhiyun * nvidia,lock, nvidia,rcv-sel, nvidia,high-speed-mode, nvidia,schmitt. 17*4882a593Smuzhiyun */ 18*4882a593Smuzhiyun #define TEGRA_PIN_DISABLE 0 19*4882a593Smuzhiyun #define TEGRA_PIN_ENABLE 1 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun #define TEGRA_PIN_PULL_NONE 0 22*4882a593Smuzhiyun #define TEGRA_PIN_PULL_DOWN 1 23*4882a593Smuzhiyun #define TEGRA_PIN_PULL_UP 2 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun /* Low power mode driver */ 26*4882a593Smuzhiyun #define TEGRA_PIN_LP_DRIVE_DIV_8 0 27*4882a593Smuzhiyun #define TEGRA_PIN_LP_DRIVE_DIV_4 1 28*4882a593Smuzhiyun #define TEGRA_PIN_LP_DRIVE_DIV_2 2 29*4882a593Smuzhiyun #define TEGRA_PIN_LP_DRIVE_DIV_1 3 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun /* Rising/Falling slew rate */ 32*4882a593Smuzhiyun #define TEGRA_PIN_SLEW_RATE_FASTEST 0 33*4882a593Smuzhiyun #define TEGRA_PIN_SLEW_RATE_FAST 1 34*4882a593Smuzhiyun #define TEGRA_PIN_SLEW_RATE_SLOW 2 35*4882a593Smuzhiyun #define TEGRA_PIN_SLEW_RATE_SLOWEST 3 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun #endif 38