1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0+ */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (C) 2016 Freescale Semiconductor, Inc. 4*4882a593Smuzhiyun * Copyright 2017~2018 NXP 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #ifndef _IMX8QXP_PADS_H 8*4882a593Smuzhiyun #define _IMX8QXP_PADS_H 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun /* pin id */ 11*4882a593Smuzhiyun #define IMX8QXP_PCIE_CTRL0_PERST_B 0 12*4882a593Smuzhiyun #define IMX8QXP_PCIE_CTRL0_CLKREQ_B 1 13*4882a593Smuzhiyun #define IMX8QXP_PCIE_CTRL0_WAKE_B 2 14*4882a593Smuzhiyun #define IMX8QXP_COMP_CTL_GPIO_1V8_3V3_PCIESEP 3 15*4882a593Smuzhiyun #define IMX8QXP_USB_SS3_TC0 4 16*4882a593Smuzhiyun #define IMX8QXP_USB_SS3_TC1 5 17*4882a593Smuzhiyun #define IMX8QXP_USB_SS3_TC2 6 18*4882a593Smuzhiyun #define IMX8QXP_USB_SS3_TC3 7 19*4882a593Smuzhiyun #define IMX8QXP_COMP_CTL_GPIO_3V3_USB3IO 8 20*4882a593Smuzhiyun #define IMX8QXP_EMMC0_CLK 9 21*4882a593Smuzhiyun #define IMX8QXP_EMMC0_CMD 10 22*4882a593Smuzhiyun #define IMX8QXP_EMMC0_DATA0 11 23*4882a593Smuzhiyun #define IMX8QXP_EMMC0_DATA1 12 24*4882a593Smuzhiyun #define IMX8QXP_EMMC0_DATA2 13 25*4882a593Smuzhiyun #define IMX8QXP_EMMC0_DATA3 14 26*4882a593Smuzhiyun #define IMX8QXP_COMP_CTL_GPIO_1V8_3V3_SD1FIX0 15 27*4882a593Smuzhiyun #define IMX8QXP_EMMC0_DATA4 16 28*4882a593Smuzhiyun #define IMX8QXP_EMMC0_DATA5 17 29*4882a593Smuzhiyun #define IMX8QXP_EMMC0_DATA6 18 30*4882a593Smuzhiyun #define IMX8QXP_EMMC0_DATA7 19 31*4882a593Smuzhiyun #define IMX8QXP_EMMC0_STROBE 20 32*4882a593Smuzhiyun #define IMX8QXP_EMMC0_RESET_B 21 33*4882a593Smuzhiyun #define IMX8QXP_COMP_CTL_GPIO_1V8_3V3_SD1FIX1 22 34*4882a593Smuzhiyun #define IMX8QXP_USDHC1_RESET_B 23 35*4882a593Smuzhiyun #define IMX8QXP_USDHC1_VSELECT 24 36*4882a593Smuzhiyun #define IMX8QXP_CTL_NAND_RE_P_N 25 37*4882a593Smuzhiyun #define IMX8QXP_USDHC1_WP 26 38*4882a593Smuzhiyun #define IMX8QXP_USDHC1_CD_B 27 39*4882a593Smuzhiyun #define IMX8QXP_CTL_NAND_DQS_P_N 28 40*4882a593Smuzhiyun #define IMX8QXP_COMP_CTL_GPIO_1V8_3V3_VSELSEP 29 41*4882a593Smuzhiyun #define IMX8QXP_USDHC1_CLK 30 42*4882a593Smuzhiyun #define IMX8QXP_USDHC1_CMD 31 43*4882a593Smuzhiyun #define IMX8QXP_USDHC1_DATA0 32 44*4882a593Smuzhiyun #define IMX8QXP_USDHC1_DATA1 33 45*4882a593Smuzhiyun #define IMX8QXP_USDHC1_DATA2 34 46*4882a593Smuzhiyun #define IMX8QXP_USDHC1_DATA3 35 47*4882a593Smuzhiyun #define IMX8QXP_COMP_CTL_GPIO_1V8_3V3_VSEL3 36 48*4882a593Smuzhiyun #define IMX8QXP_ENET0_RGMII_TXC 37 49*4882a593Smuzhiyun #define IMX8QXP_ENET0_RGMII_TX_CTL 38 50*4882a593Smuzhiyun #define IMX8QXP_ENET0_RGMII_TXD0 39 51*4882a593Smuzhiyun #define IMX8QXP_ENET0_RGMII_TXD1 40 52*4882a593Smuzhiyun #define IMX8QXP_ENET0_RGMII_TXD2 41 53*4882a593Smuzhiyun #define IMX8QXP_ENET0_RGMII_TXD3 42 54*4882a593Smuzhiyun #define IMX8QXP_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0 43 55*4882a593Smuzhiyun #define IMX8QXP_ENET0_RGMII_RXC 44 56*4882a593Smuzhiyun #define IMX8QXP_ENET0_RGMII_RX_CTL 45 57*4882a593Smuzhiyun #define IMX8QXP_ENET0_RGMII_RXD0 46 58*4882a593Smuzhiyun #define IMX8QXP_ENET0_RGMII_RXD1 47 59*4882a593Smuzhiyun #define IMX8QXP_ENET0_RGMII_RXD2 48 60*4882a593Smuzhiyun #define IMX8QXP_ENET0_RGMII_RXD3 49 61*4882a593Smuzhiyun #define IMX8QXP_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1 50 62*4882a593Smuzhiyun #define IMX8QXP_ENET0_REFCLK_125M_25M 51 63*4882a593Smuzhiyun #define IMX8QXP_ENET0_MDIO 52 64*4882a593Smuzhiyun #define IMX8QXP_ENET0_MDC 53 65*4882a593Smuzhiyun #define IMX8QXP_COMP_CTL_GPIO_1V8_3V3_GPIOCT 54 66*4882a593Smuzhiyun #define IMX8QXP_ESAI0_FSR 55 67*4882a593Smuzhiyun #define IMX8QXP_ESAI0_FST 56 68*4882a593Smuzhiyun #define IMX8QXP_ESAI0_SCKR 57 69*4882a593Smuzhiyun #define IMX8QXP_ESAI0_SCKT 58 70*4882a593Smuzhiyun #define IMX8QXP_ESAI0_TX0 59 71*4882a593Smuzhiyun #define IMX8QXP_ESAI0_TX1 60 72*4882a593Smuzhiyun #define IMX8QXP_ESAI0_TX2_RX3 61 73*4882a593Smuzhiyun #define IMX8QXP_ESAI0_TX3_RX2 62 74*4882a593Smuzhiyun #define IMX8QXP_ESAI0_TX4_RX1 63 75*4882a593Smuzhiyun #define IMX8QXP_ESAI0_TX5_RX0 64 76*4882a593Smuzhiyun #define IMX8QXP_SPDIF0_RX 65 77*4882a593Smuzhiyun #define IMX8QXP_SPDIF0_TX 66 78*4882a593Smuzhiyun #define IMX8QXP_SPDIF0_EXT_CLK 67 79*4882a593Smuzhiyun #define IMX8QXP_COMP_CTL_GPIO_1V8_3V3_GPIORHB 68 80*4882a593Smuzhiyun #define IMX8QXP_SPI3_SCK 69 81*4882a593Smuzhiyun #define IMX8QXP_SPI3_SDO 70 82*4882a593Smuzhiyun #define IMX8QXP_SPI3_SDI 71 83*4882a593Smuzhiyun #define IMX8QXP_SPI3_CS0 72 84*4882a593Smuzhiyun #define IMX8QXP_SPI3_CS1 73 85*4882a593Smuzhiyun #define IMX8QXP_MCLK_IN1 74 86*4882a593Smuzhiyun #define IMX8QXP_MCLK_IN0 75 87*4882a593Smuzhiyun #define IMX8QXP_MCLK_OUT0 76 88*4882a593Smuzhiyun #define IMX8QXP_UART1_TX 77 89*4882a593Smuzhiyun #define IMX8QXP_UART1_RX 78 90*4882a593Smuzhiyun #define IMX8QXP_UART1_RTS_B 79 91*4882a593Smuzhiyun #define IMX8QXP_UART1_CTS_B 80 92*4882a593Smuzhiyun #define IMX8QXP_COMP_CTL_GPIO_1V8_3V3_GPIORHK 81 93*4882a593Smuzhiyun #define IMX8QXP_SAI0_TXD 82 94*4882a593Smuzhiyun #define IMX8QXP_SAI0_TXC 83 95*4882a593Smuzhiyun #define IMX8QXP_SAI0_RXD 84 96*4882a593Smuzhiyun #define IMX8QXP_SAI0_TXFS 85 97*4882a593Smuzhiyun #define IMX8QXP_SAI1_RXD 86 98*4882a593Smuzhiyun #define IMX8QXP_SAI1_RXC 87 99*4882a593Smuzhiyun #define IMX8QXP_SAI1_RXFS 88 100*4882a593Smuzhiyun #define IMX8QXP_SPI2_CS0 89 101*4882a593Smuzhiyun #define IMX8QXP_SPI2_SDO 90 102*4882a593Smuzhiyun #define IMX8QXP_SPI2_SDI 91 103*4882a593Smuzhiyun #define IMX8QXP_SPI2_SCK 92 104*4882a593Smuzhiyun #define IMX8QXP_SPI0_SCK 93 105*4882a593Smuzhiyun #define IMX8QXP_SPI0_SDI 94 106*4882a593Smuzhiyun #define IMX8QXP_SPI0_SDO 95 107*4882a593Smuzhiyun #define IMX8QXP_SPI0_CS1 96 108*4882a593Smuzhiyun #define IMX8QXP_SPI0_CS0 97 109*4882a593Smuzhiyun #define IMX8QXP_COMP_CTL_GPIO_1V8_3V3_GPIORHT 98 110*4882a593Smuzhiyun #define IMX8QXP_ADC_IN1 99 111*4882a593Smuzhiyun #define IMX8QXP_ADC_IN0 100 112*4882a593Smuzhiyun #define IMX8QXP_ADC_IN3 101 113*4882a593Smuzhiyun #define IMX8QXP_ADC_IN2 102 114*4882a593Smuzhiyun #define IMX8QXP_ADC_IN5 103 115*4882a593Smuzhiyun #define IMX8QXP_ADC_IN4 104 116*4882a593Smuzhiyun #define IMX8QXP_FLEXCAN0_RX 105 117*4882a593Smuzhiyun #define IMX8QXP_FLEXCAN0_TX 106 118*4882a593Smuzhiyun #define IMX8QXP_FLEXCAN1_RX 107 119*4882a593Smuzhiyun #define IMX8QXP_FLEXCAN1_TX 108 120*4882a593Smuzhiyun #define IMX8QXP_FLEXCAN2_RX 109 121*4882a593Smuzhiyun #define IMX8QXP_FLEXCAN2_TX 110 122*4882a593Smuzhiyun #define IMX8QXP_UART0_RX 111 123*4882a593Smuzhiyun #define IMX8QXP_UART0_TX 112 124*4882a593Smuzhiyun #define IMX8QXP_UART2_TX 113 125*4882a593Smuzhiyun #define IMX8QXP_UART2_RX 114 126*4882a593Smuzhiyun #define IMX8QXP_COMP_CTL_GPIO_1V8_3V3_GPIOLH 115 127*4882a593Smuzhiyun #define IMX8QXP_MIPI_DSI0_I2C0_SCL 116 128*4882a593Smuzhiyun #define IMX8QXP_MIPI_DSI0_I2C0_SDA 117 129*4882a593Smuzhiyun #define IMX8QXP_MIPI_DSI0_GPIO0_00 118 130*4882a593Smuzhiyun #define IMX8QXP_MIPI_DSI0_GPIO0_01 119 131*4882a593Smuzhiyun #define IMX8QXP_MIPI_DSI1_I2C0_SCL 120 132*4882a593Smuzhiyun #define IMX8QXP_MIPI_DSI1_I2C0_SDA 121 133*4882a593Smuzhiyun #define IMX8QXP_MIPI_DSI1_GPIO0_00 122 134*4882a593Smuzhiyun #define IMX8QXP_MIPI_DSI1_GPIO0_01 123 135*4882a593Smuzhiyun #define IMX8QXP_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO 124 136*4882a593Smuzhiyun #define IMX8QXP_JTAG_TRST_B 125 137*4882a593Smuzhiyun #define IMX8QXP_PMIC_I2C_SCL 126 138*4882a593Smuzhiyun #define IMX8QXP_PMIC_I2C_SDA 127 139*4882a593Smuzhiyun #define IMX8QXP_PMIC_INT_B 128 140*4882a593Smuzhiyun #define IMX8QXP_SCU_GPIO0_00 129 141*4882a593Smuzhiyun #define IMX8QXP_SCU_GPIO0_01 130 142*4882a593Smuzhiyun #define IMX8QXP_SCU_PMIC_STANDBY 131 143*4882a593Smuzhiyun #define IMX8QXP_SCU_BOOT_MODE0 132 144*4882a593Smuzhiyun #define IMX8QXP_SCU_BOOT_MODE1 133 145*4882a593Smuzhiyun #define IMX8QXP_SCU_BOOT_MODE2 134 146*4882a593Smuzhiyun #define IMX8QXP_SCU_BOOT_MODE3 135 147*4882a593Smuzhiyun #define IMX8QXP_CSI_D00 136 148*4882a593Smuzhiyun #define IMX8QXP_CSI_D01 137 149*4882a593Smuzhiyun #define IMX8QXP_CSI_D02 138 150*4882a593Smuzhiyun #define IMX8QXP_CSI_D03 139 151*4882a593Smuzhiyun #define IMX8QXP_CSI_D04 140 152*4882a593Smuzhiyun #define IMX8QXP_CSI_D05 141 153*4882a593Smuzhiyun #define IMX8QXP_CSI_D06 142 154*4882a593Smuzhiyun #define IMX8QXP_CSI_D07 143 155*4882a593Smuzhiyun #define IMX8QXP_CSI_HSYNC 144 156*4882a593Smuzhiyun #define IMX8QXP_CSI_VSYNC 145 157*4882a593Smuzhiyun #define IMX8QXP_CSI_PCLK 146 158*4882a593Smuzhiyun #define IMX8QXP_CSI_MCLK 147 159*4882a593Smuzhiyun #define IMX8QXP_CSI_EN 148 160*4882a593Smuzhiyun #define IMX8QXP_CSI_RESET 149 161*4882a593Smuzhiyun #define IMX8QXP_COMP_CTL_GPIO_1V8_3V3_GPIORHD 150 162*4882a593Smuzhiyun #define IMX8QXP_MIPI_CSI0_MCLK_OUT 151 163*4882a593Smuzhiyun #define IMX8QXP_MIPI_CSI0_I2C0_SCL 152 164*4882a593Smuzhiyun #define IMX8QXP_MIPI_CSI0_I2C0_SDA 153 165*4882a593Smuzhiyun #define IMX8QXP_MIPI_CSI0_GPIO0_01 154 166*4882a593Smuzhiyun #define IMX8QXP_MIPI_CSI0_GPIO0_00 155 167*4882a593Smuzhiyun #define IMX8QXP_QSPI0A_DATA0 156 168*4882a593Smuzhiyun #define IMX8QXP_QSPI0A_DATA1 157 169*4882a593Smuzhiyun #define IMX8QXP_QSPI0A_DATA2 158 170*4882a593Smuzhiyun #define IMX8QXP_QSPI0A_DATA3 159 171*4882a593Smuzhiyun #define IMX8QXP_QSPI0A_DQS 160 172*4882a593Smuzhiyun #define IMX8QXP_QSPI0A_SS0_B 161 173*4882a593Smuzhiyun #define IMX8QXP_QSPI0A_SS1_B 162 174*4882a593Smuzhiyun #define IMX8QXP_QSPI0A_SCLK 163 175*4882a593Smuzhiyun #define IMX8QXP_COMP_CTL_GPIO_1V8_3V3_QSPI0A 164 176*4882a593Smuzhiyun #define IMX8QXP_QSPI0B_SCLK 165 177*4882a593Smuzhiyun #define IMX8QXP_QSPI0B_DATA0 166 178*4882a593Smuzhiyun #define IMX8QXP_QSPI0B_DATA1 167 179*4882a593Smuzhiyun #define IMX8QXP_QSPI0B_DATA2 168 180*4882a593Smuzhiyun #define IMX8QXP_QSPI0B_DATA3 169 181*4882a593Smuzhiyun #define IMX8QXP_QSPI0B_DQS 170 182*4882a593Smuzhiyun #define IMX8QXP_QSPI0B_SS0_B 171 183*4882a593Smuzhiyun #define IMX8QXP_QSPI0B_SS1_B 172 184*4882a593Smuzhiyun #define IMX8QXP_COMP_CTL_GPIO_1V8_3V3_QSPI0B 173 185*4882a593Smuzhiyun 186*4882a593Smuzhiyun /* 187*4882a593Smuzhiyun * format: <pin_id mux_mode> 188*4882a593Smuzhiyun */ 189*4882a593Smuzhiyun #define IMX8QXP_PCIE_CTRL0_PERST_B_HSIO_PCIE0_PERST_B IMX8QXP_PCIE_CTRL0_PERST_B 0 190*4882a593Smuzhiyun #define IMX8QXP_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO00 IMX8QXP_PCIE_CTRL0_PERST_B 4 191*4882a593Smuzhiyun #define IMX8QXP_PCIE_CTRL0_CLKREQ_B_HSIO_PCIE0_CLKREQ_B IMX8QXP_PCIE_CTRL0_CLKREQ_B 0 192*4882a593Smuzhiyun #define IMX8QXP_PCIE_CTRL0_CLKREQ_B_LSIO_GPIO4_IO01 IMX8QXP_PCIE_CTRL0_CLKREQ_B 4 193*4882a593Smuzhiyun #define IMX8QXP_PCIE_CTRL0_WAKE_B_HSIO_PCIE0_WAKE_B IMX8QXP_PCIE_CTRL0_WAKE_B 0 194*4882a593Smuzhiyun #define IMX8QXP_PCIE_CTRL0_WAKE_B_LSIO_GPIO4_IO02 IMX8QXP_PCIE_CTRL0_WAKE_B 4 195*4882a593Smuzhiyun #define IMX8QXP_USB_SS3_TC0_ADMA_I2C1_SCL IMX8QXP_USB_SS3_TC0 0 196*4882a593Smuzhiyun #define IMX8QXP_USB_SS3_TC0_CONN_USB_OTG1_PWR IMX8QXP_USB_SS3_TC0 1 197*4882a593Smuzhiyun #define IMX8QXP_USB_SS3_TC0_CONN_USB_OTG2_PWR IMX8QXP_USB_SS3_TC0 2 198*4882a593Smuzhiyun #define IMX8QXP_USB_SS3_TC0_LSIO_GPIO4_IO03 IMX8QXP_USB_SS3_TC0 4 199*4882a593Smuzhiyun #define IMX8QXP_USB_SS3_TC1_ADMA_I2C1_SCL IMX8QXP_USB_SS3_TC1 0 200*4882a593Smuzhiyun #define IMX8QXP_USB_SS3_TC1_CONN_USB_OTG2_PWR IMX8QXP_USB_SS3_TC1 1 201*4882a593Smuzhiyun #define IMX8QXP_USB_SS3_TC1_LSIO_GPIO4_IO04 IMX8QXP_USB_SS3_TC1 4 202*4882a593Smuzhiyun #define IMX8QXP_USB_SS3_TC2_ADMA_I2C1_SDA IMX8QXP_USB_SS3_TC2 0 203*4882a593Smuzhiyun #define IMX8QXP_USB_SS3_TC2_CONN_USB_OTG1_OC IMX8QXP_USB_SS3_TC2 1 204*4882a593Smuzhiyun #define IMX8QXP_USB_SS3_TC2_CONN_USB_OTG2_OC IMX8QXP_USB_SS3_TC2 2 205*4882a593Smuzhiyun #define IMX8QXP_USB_SS3_TC2_LSIO_GPIO4_IO05 IMX8QXP_USB_SS3_TC2 4 206*4882a593Smuzhiyun #define IMX8QXP_USB_SS3_TC3_ADMA_I2C1_SDA IMX8QXP_USB_SS3_TC3 0 207*4882a593Smuzhiyun #define IMX8QXP_USB_SS3_TC3_CONN_USB_OTG2_OC IMX8QXP_USB_SS3_TC3 1 208*4882a593Smuzhiyun #define IMX8QXP_USB_SS3_TC3_LSIO_GPIO4_IO06 IMX8QXP_USB_SS3_TC3 4 209*4882a593Smuzhiyun #define IMX8QXP_EMMC0_CLK_CONN_EMMC0_CLK IMX8QXP_EMMC0_CLK 0 210*4882a593Smuzhiyun #define IMX8QXP_EMMC0_CLK_CONN_NAND_READY_B IMX8QXP_EMMC0_CLK 1 211*4882a593Smuzhiyun #define IMX8QXP_EMMC0_CLK_LSIO_GPIO4_IO07 IMX8QXP_EMMC0_CLK 4 212*4882a593Smuzhiyun #define IMX8QXP_EMMC0_CMD_CONN_EMMC0_CMD IMX8QXP_EMMC0_CMD 0 213*4882a593Smuzhiyun #define IMX8QXP_EMMC0_CMD_CONN_NAND_DQS IMX8QXP_EMMC0_CMD 1 214*4882a593Smuzhiyun #define IMX8QXP_EMMC0_CMD_LSIO_GPIO4_IO08 IMX8QXP_EMMC0_CMD 4 215*4882a593Smuzhiyun #define IMX8QXP_EMMC0_DATA0_CONN_EMMC0_DATA0 IMX8QXP_EMMC0_DATA0 0 216*4882a593Smuzhiyun #define IMX8QXP_EMMC0_DATA0_CONN_NAND_DATA00 IMX8QXP_EMMC0_DATA0 1 217*4882a593Smuzhiyun #define IMX8QXP_EMMC0_DATA0_LSIO_GPIO4_IO09 IMX8QXP_EMMC0_DATA0 4 218*4882a593Smuzhiyun #define IMX8QXP_EMMC0_DATA1_CONN_EMMC0_DATA1 IMX8QXP_EMMC0_DATA1 0 219*4882a593Smuzhiyun #define IMX8QXP_EMMC0_DATA1_CONN_NAND_DATA01 IMX8QXP_EMMC0_DATA1 1 220*4882a593Smuzhiyun #define IMX8QXP_EMMC0_DATA1_LSIO_GPIO4_IO10 IMX8QXP_EMMC0_DATA1 4 221*4882a593Smuzhiyun #define IMX8QXP_EMMC0_DATA2_CONN_EMMC0_DATA2 IMX8QXP_EMMC0_DATA2 0 222*4882a593Smuzhiyun #define IMX8QXP_EMMC0_DATA2_CONN_NAND_DATA02 IMX8QXP_EMMC0_DATA2 1 223*4882a593Smuzhiyun #define IMX8QXP_EMMC0_DATA2_LSIO_GPIO4_IO11 IMX8QXP_EMMC0_DATA2 4 224*4882a593Smuzhiyun #define IMX8QXP_EMMC0_DATA3_CONN_EMMC0_DATA3 IMX8QXP_EMMC0_DATA3 0 225*4882a593Smuzhiyun #define IMX8QXP_EMMC0_DATA3_CONN_NAND_DATA03 IMX8QXP_EMMC0_DATA3 1 226*4882a593Smuzhiyun #define IMX8QXP_EMMC0_DATA3_LSIO_GPIO4_IO12 IMX8QXP_EMMC0_DATA3 4 227*4882a593Smuzhiyun #define IMX8QXP_EMMC0_DATA4_CONN_EMMC0_DATA4 IMX8QXP_EMMC0_DATA4 0 228*4882a593Smuzhiyun #define IMX8QXP_EMMC0_DATA4_CONN_NAND_DATA04 IMX8QXP_EMMC0_DATA4 1 229*4882a593Smuzhiyun #define IMX8QXP_EMMC0_DATA4_CONN_EMMC0_WP IMX8QXP_EMMC0_DATA4 3 230*4882a593Smuzhiyun #define IMX8QXP_EMMC0_DATA4_LSIO_GPIO4_IO13 IMX8QXP_EMMC0_DATA4 4 231*4882a593Smuzhiyun #define IMX8QXP_EMMC0_DATA5_CONN_EMMC0_DATA5 IMX8QXP_EMMC0_DATA5 0 232*4882a593Smuzhiyun #define IMX8QXP_EMMC0_DATA5_CONN_NAND_DATA05 IMX8QXP_EMMC0_DATA5 1 233*4882a593Smuzhiyun #define IMX8QXP_EMMC0_DATA5_CONN_EMMC0_VSELECT IMX8QXP_EMMC0_DATA5 3 234*4882a593Smuzhiyun #define IMX8QXP_EMMC0_DATA5_LSIO_GPIO4_IO14 IMX8QXP_EMMC0_DATA5 4 235*4882a593Smuzhiyun #define IMX8QXP_EMMC0_DATA6_CONN_EMMC0_DATA6 IMX8QXP_EMMC0_DATA6 0 236*4882a593Smuzhiyun #define IMX8QXP_EMMC0_DATA6_CONN_NAND_DATA06 IMX8QXP_EMMC0_DATA6 1 237*4882a593Smuzhiyun #define IMX8QXP_EMMC0_DATA6_CONN_MLB_CLK IMX8QXP_EMMC0_DATA6 3 238*4882a593Smuzhiyun #define IMX8QXP_EMMC0_DATA6_LSIO_GPIO4_IO15 IMX8QXP_EMMC0_DATA6 4 239*4882a593Smuzhiyun #define IMX8QXP_EMMC0_DATA7_CONN_EMMC0_DATA7 IMX8QXP_EMMC0_DATA7 0 240*4882a593Smuzhiyun #define IMX8QXP_EMMC0_DATA7_CONN_NAND_DATA07 IMX8QXP_EMMC0_DATA7 1 241*4882a593Smuzhiyun #define IMX8QXP_EMMC0_DATA7_CONN_MLB_SIG IMX8QXP_EMMC0_DATA7 3 242*4882a593Smuzhiyun #define IMX8QXP_EMMC0_DATA7_LSIO_GPIO4_IO16 IMX8QXP_EMMC0_DATA7 4 243*4882a593Smuzhiyun #define IMX8QXP_EMMC0_STROBE_CONN_EMMC0_STROBE IMX8QXP_EMMC0_STROBE 0 244*4882a593Smuzhiyun #define IMX8QXP_EMMC0_STROBE_CONN_NAND_CLE IMX8QXP_EMMC0_STROBE 1 245*4882a593Smuzhiyun #define IMX8QXP_EMMC0_STROBE_CONN_MLB_DATA IMX8QXP_EMMC0_STROBE 3 246*4882a593Smuzhiyun #define IMX8QXP_EMMC0_STROBE_LSIO_GPIO4_IO17 IMX8QXP_EMMC0_STROBE 4 247*4882a593Smuzhiyun #define IMX8QXP_EMMC0_RESET_B_CONN_EMMC0_RESET_B IMX8QXP_EMMC0_RESET_B 0 248*4882a593Smuzhiyun #define IMX8QXP_EMMC0_RESET_B_CONN_NAND_WP_B IMX8QXP_EMMC0_RESET_B 1 249*4882a593Smuzhiyun #define IMX8QXP_EMMC0_RESET_B_LSIO_GPIO4_IO18 IMX8QXP_EMMC0_RESET_B 4 250*4882a593Smuzhiyun #define IMX8QXP_USDHC1_RESET_B_CONN_USDHC1_RESET_B IMX8QXP_USDHC1_RESET_B 0 251*4882a593Smuzhiyun #define IMX8QXP_USDHC1_RESET_B_CONN_NAND_RE_N IMX8QXP_USDHC1_RESET_B 1 252*4882a593Smuzhiyun #define IMX8QXP_USDHC1_RESET_B_ADMA_SPI2_SCK IMX8QXP_USDHC1_RESET_B 2 253*4882a593Smuzhiyun #define IMX8QXP_USDHC1_RESET_B_LSIO_GPIO4_IO19 IMX8QXP_USDHC1_RESET_B 4 254*4882a593Smuzhiyun #define IMX8QXP_USDHC1_VSELECT_CONN_USDHC1_VSELECT IMX8QXP_USDHC1_VSELECT 0 255*4882a593Smuzhiyun #define IMX8QXP_USDHC1_VSELECT_CONN_NAND_RE_P IMX8QXP_USDHC1_VSELECT 1 256*4882a593Smuzhiyun #define IMX8QXP_USDHC1_VSELECT_ADMA_SPI2_SDO IMX8QXP_USDHC1_VSELECT 2 257*4882a593Smuzhiyun #define IMX8QXP_USDHC1_VSELECT_CONN_NAND_RE_B IMX8QXP_USDHC1_VSELECT 3 258*4882a593Smuzhiyun #define IMX8QXP_USDHC1_VSELECT_LSIO_GPIO4_IO20 IMX8QXP_USDHC1_VSELECT 4 259*4882a593Smuzhiyun #define IMX8QXP_USDHC1_WP_CONN_USDHC1_WP IMX8QXP_USDHC1_WP 0 260*4882a593Smuzhiyun #define IMX8QXP_USDHC1_WP_CONN_NAND_DQS_N IMX8QXP_USDHC1_WP 1 261*4882a593Smuzhiyun #define IMX8QXP_USDHC1_WP_ADMA_SPI2_SDI IMX8QXP_USDHC1_WP 2 262*4882a593Smuzhiyun #define IMX8QXP_USDHC1_WP_LSIO_GPIO4_IO21 IMX8QXP_USDHC1_WP 4 263*4882a593Smuzhiyun #define IMX8QXP_USDHC1_CD_B_CONN_USDHC1_CD_B IMX8QXP_USDHC1_CD_B 0 264*4882a593Smuzhiyun #define IMX8QXP_USDHC1_CD_B_CONN_NAND_DQS_P IMX8QXP_USDHC1_CD_B 1 265*4882a593Smuzhiyun #define IMX8QXP_USDHC1_CD_B_ADMA_SPI2_CS0 IMX8QXP_USDHC1_CD_B 2 266*4882a593Smuzhiyun #define IMX8QXP_USDHC1_CD_B_CONN_NAND_DQS IMX8QXP_USDHC1_CD_B 3 267*4882a593Smuzhiyun #define IMX8QXP_USDHC1_CD_B_LSIO_GPIO4_IO22 IMX8QXP_USDHC1_CD_B 4 268*4882a593Smuzhiyun #define IMX8QXP_USDHC1_CLK_CONN_USDHC1_CLK IMX8QXP_USDHC1_CLK 0 269*4882a593Smuzhiyun #define IMX8QXP_USDHC1_CLK_ADMA_UART3_RX IMX8QXP_USDHC1_CLK 2 270*4882a593Smuzhiyun #define IMX8QXP_USDHC1_CLK_LSIO_GPIO4_IO23 IMX8QXP_USDHC1_CLK 4 271*4882a593Smuzhiyun #define IMX8QXP_USDHC1_CMD_CONN_USDHC1_CMD IMX8QXP_USDHC1_CMD 0 272*4882a593Smuzhiyun #define IMX8QXP_USDHC1_CMD_CONN_NAND_CE0_B IMX8QXP_USDHC1_CMD 1 273*4882a593Smuzhiyun #define IMX8QXP_USDHC1_CMD_ADMA_MQS_R IMX8QXP_USDHC1_CMD 2 274*4882a593Smuzhiyun #define IMX8QXP_USDHC1_CMD_LSIO_GPIO4_IO24 IMX8QXP_USDHC1_CMD 4 275*4882a593Smuzhiyun #define IMX8QXP_USDHC1_DATA0_CONN_USDHC1_DATA0 IMX8QXP_USDHC1_DATA0 0 276*4882a593Smuzhiyun #define IMX8QXP_USDHC1_DATA0_CONN_NAND_CE1_B IMX8QXP_USDHC1_DATA0 1 277*4882a593Smuzhiyun #define IMX8QXP_USDHC1_DATA0_ADMA_MQS_L IMX8QXP_USDHC1_DATA0 2 278*4882a593Smuzhiyun #define IMX8QXP_USDHC1_DATA0_LSIO_GPIO4_IO25 IMX8QXP_USDHC1_DATA0 4 279*4882a593Smuzhiyun #define IMX8QXP_USDHC1_DATA1_CONN_USDHC1_DATA1 IMX8QXP_USDHC1_DATA1 0 280*4882a593Smuzhiyun #define IMX8QXP_USDHC1_DATA1_CONN_NAND_RE_B IMX8QXP_USDHC1_DATA1 1 281*4882a593Smuzhiyun #define IMX8QXP_USDHC1_DATA1_ADMA_UART3_TX IMX8QXP_USDHC1_DATA1 2 282*4882a593Smuzhiyun #define IMX8QXP_USDHC1_DATA1_LSIO_GPIO4_IO26 IMX8QXP_USDHC1_DATA1 4 283*4882a593Smuzhiyun #define IMX8QXP_USDHC1_DATA2_CONN_USDHC1_DATA2 IMX8QXP_USDHC1_DATA2 0 284*4882a593Smuzhiyun #define IMX8QXP_USDHC1_DATA2_CONN_NAND_WE_B IMX8QXP_USDHC1_DATA2 1 285*4882a593Smuzhiyun #define IMX8QXP_USDHC1_DATA2_ADMA_UART3_CTS_B IMX8QXP_USDHC1_DATA2 2 286*4882a593Smuzhiyun #define IMX8QXP_USDHC1_DATA2_LSIO_GPIO4_IO27 IMX8QXP_USDHC1_DATA2 4 287*4882a593Smuzhiyun #define IMX8QXP_USDHC1_DATA3_CONN_USDHC1_DATA3 IMX8QXP_USDHC1_DATA3 0 288*4882a593Smuzhiyun #define IMX8QXP_USDHC1_DATA3_CONN_NAND_ALE IMX8QXP_USDHC1_DATA3 1 289*4882a593Smuzhiyun #define IMX8QXP_USDHC1_DATA3_ADMA_UART3_RTS_B IMX8QXP_USDHC1_DATA3 2 290*4882a593Smuzhiyun #define IMX8QXP_USDHC1_DATA3_LSIO_GPIO4_IO28 IMX8QXP_USDHC1_DATA3 4 291*4882a593Smuzhiyun #define IMX8QXP_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC IMX8QXP_ENET0_RGMII_TXC 0 292*4882a593Smuzhiyun #define IMX8QXP_ENET0_RGMII_TXC_CONN_ENET0_RCLK50M_OUT IMX8QXP_ENET0_RGMII_TXC 1 293*4882a593Smuzhiyun #define IMX8QXP_ENET0_RGMII_TXC_CONN_ENET0_RCLK50M_IN IMX8QXP_ENET0_RGMII_TXC 2 294*4882a593Smuzhiyun #define IMX8QXP_ENET0_RGMII_TXC_CONN_NAND_CE1_B IMX8QXP_ENET0_RGMII_TXC 3 295*4882a593Smuzhiyun #define IMX8QXP_ENET0_RGMII_TXC_LSIO_GPIO4_IO29 IMX8QXP_ENET0_RGMII_TXC 4 296*4882a593Smuzhiyun #define IMX8QXP_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL IMX8QXP_ENET0_RGMII_TX_CTL 0 297*4882a593Smuzhiyun #define IMX8QXP_ENET0_RGMII_TX_CTL_CONN_USDHC1_RESET_B IMX8QXP_ENET0_RGMII_TX_CTL 3 298*4882a593Smuzhiyun #define IMX8QXP_ENET0_RGMII_TX_CTL_LSIO_GPIO4_IO30 IMX8QXP_ENET0_RGMII_TX_CTL 4 299*4882a593Smuzhiyun #define IMX8QXP_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 IMX8QXP_ENET0_RGMII_TXD0 0 300*4882a593Smuzhiyun #define IMX8QXP_ENET0_RGMII_TXD0_CONN_USDHC1_VSELECT IMX8QXP_ENET0_RGMII_TXD0 3 301*4882a593Smuzhiyun #define IMX8QXP_ENET0_RGMII_TXD0_LSIO_GPIO4_IO31 IMX8QXP_ENET0_RGMII_TXD0 4 302*4882a593Smuzhiyun #define IMX8QXP_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 IMX8QXP_ENET0_RGMII_TXD1 0 303*4882a593Smuzhiyun #define IMX8QXP_ENET0_RGMII_TXD1_CONN_USDHC1_WP IMX8QXP_ENET0_RGMII_TXD1 3 304*4882a593Smuzhiyun #define IMX8QXP_ENET0_RGMII_TXD1_LSIO_GPIO5_IO00 IMX8QXP_ENET0_RGMII_TXD1 4 305*4882a593Smuzhiyun #define IMX8QXP_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 IMX8QXP_ENET0_RGMII_TXD2 0 306*4882a593Smuzhiyun #define IMX8QXP_ENET0_RGMII_TXD2_CONN_MLB_CLK IMX8QXP_ENET0_RGMII_TXD2 1 307*4882a593Smuzhiyun #define IMX8QXP_ENET0_RGMII_TXD2_CONN_NAND_CE0_B IMX8QXP_ENET0_RGMII_TXD2 2 308*4882a593Smuzhiyun #define IMX8QXP_ENET0_RGMII_TXD2_CONN_USDHC1_CD_B IMX8QXP_ENET0_RGMII_TXD2 3 309*4882a593Smuzhiyun #define IMX8QXP_ENET0_RGMII_TXD2_LSIO_GPIO5_IO01 IMX8QXP_ENET0_RGMII_TXD2 4 310*4882a593Smuzhiyun #define IMX8QXP_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 IMX8QXP_ENET0_RGMII_TXD3 0 311*4882a593Smuzhiyun #define IMX8QXP_ENET0_RGMII_TXD3_CONN_MLB_SIG IMX8QXP_ENET0_RGMII_TXD3 1 312*4882a593Smuzhiyun #define IMX8QXP_ENET0_RGMII_TXD3_CONN_NAND_RE_B IMX8QXP_ENET0_RGMII_TXD3 2 313*4882a593Smuzhiyun #define IMX8QXP_ENET0_RGMII_TXD3_LSIO_GPIO5_IO02 IMX8QXP_ENET0_RGMII_TXD3 4 314*4882a593Smuzhiyun #define IMX8QXP_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC IMX8QXP_ENET0_RGMII_RXC 0 315*4882a593Smuzhiyun #define IMX8QXP_ENET0_RGMII_RXC_CONN_MLB_DATA IMX8QXP_ENET0_RGMII_RXC 1 316*4882a593Smuzhiyun #define IMX8QXP_ENET0_RGMII_RXC_CONN_NAND_WE_B IMX8QXP_ENET0_RGMII_RXC 2 317*4882a593Smuzhiyun #define IMX8QXP_ENET0_RGMII_RXC_CONN_USDHC1_CLK IMX8QXP_ENET0_RGMII_RXC 3 318*4882a593Smuzhiyun #define IMX8QXP_ENET0_RGMII_RXC_LSIO_GPIO5_IO03 IMX8QXP_ENET0_RGMII_RXC 4 319*4882a593Smuzhiyun #define IMX8QXP_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL IMX8QXP_ENET0_RGMII_RX_CTL 0 320*4882a593Smuzhiyun #define IMX8QXP_ENET0_RGMII_RX_CTL_CONN_USDHC1_CMD IMX8QXP_ENET0_RGMII_RX_CTL 3 321*4882a593Smuzhiyun #define IMX8QXP_ENET0_RGMII_RX_CTL_LSIO_GPIO5_IO04 IMX8QXP_ENET0_RGMII_RX_CTL 4 322*4882a593Smuzhiyun #define IMX8QXP_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 IMX8QXP_ENET0_RGMII_RXD0 0 323*4882a593Smuzhiyun #define IMX8QXP_ENET0_RGMII_RXD0_CONN_USDHC1_DATA0 IMX8QXP_ENET0_RGMII_RXD0 3 324*4882a593Smuzhiyun #define IMX8QXP_ENET0_RGMII_RXD0_LSIO_GPIO5_IO05 IMX8QXP_ENET0_RGMII_RXD0 4 325*4882a593Smuzhiyun #define IMX8QXP_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 IMX8QXP_ENET0_RGMII_RXD1 0 326*4882a593Smuzhiyun #define IMX8QXP_ENET0_RGMII_RXD1_CONN_USDHC1_DATA1 IMX8QXP_ENET0_RGMII_RXD1 3 327*4882a593Smuzhiyun #define IMX8QXP_ENET0_RGMII_RXD1_LSIO_GPIO5_IO06 IMX8QXP_ENET0_RGMII_RXD1 4 328*4882a593Smuzhiyun #define IMX8QXP_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 IMX8QXP_ENET0_RGMII_RXD2 0 329*4882a593Smuzhiyun #define IMX8QXP_ENET0_RGMII_RXD2_CONN_ENET0_RMII_RX_ER IMX8QXP_ENET0_RGMII_RXD2 1 330*4882a593Smuzhiyun #define IMX8QXP_ENET0_RGMII_RXD2_CONN_USDHC1_DATA2 IMX8QXP_ENET0_RGMII_RXD2 3 331*4882a593Smuzhiyun #define IMX8QXP_ENET0_RGMII_RXD2_LSIO_GPIO5_IO07 IMX8QXP_ENET0_RGMII_RXD2 4 332*4882a593Smuzhiyun #define IMX8QXP_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 IMX8QXP_ENET0_RGMII_RXD3 0 333*4882a593Smuzhiyun #define IMX8QXP_ENET0_RGMII_RXD3_CONN_NAND_ALE IMX8QXP_ENET0_RGMII_RXD3 2 334*4882a593Smuzhiyun #define IMX8QXP_ENET0_RGMII_RXD3_CONN_USDHC1_DATA3 IMX8QXP_ENET0_RGMII_RXD3 3 335*4882a593Smuzhiyun #define IMX8QXP_ENET0_RGMII_RXD3_LSIO_GPIO5_IO08 IMX8QXP_ENET0_RGMII_RXD3 4 336*4882a593Smuzhiyun #define IMX8QXP_ENET0_REFCLK_125M_25M_CONN_ENET0_REFCLK_125M_25M IMX8QXP_ENET0_REFCLK_125M_25M 0 337*4882a593Smuzhiyun #define IMX8QXP_ENET0_REFCLK_125M_25M_CONN_ENET0_PPS IMX8QXP_ENET0_REFCLK_125M_25M 1 338*4882a593Smuzhiyun #define IMX8QXP_ENET0_REFCLK_125M_25M_CONN_ENET1_PPS IMX8QXP_ENET0_REFCLK_125M_25M 2 339*4882a593Smuzhiyun #define IMX8QXP_ENET0_REFCLK_125M_25M_LSIO_GPIO5_IO09 IMX8QXP_ENET0_REFCLK_125M_25M 4 340*4882a593Smuzhiyun #define IMX8QXP_ENET0_MDIO_CONN_ENET0_MDIO IMX8QXP_ENET0_MDIO 0 341*4882a593Smuzhiyun #define IMX8QXP_ENET0_MDIO_ADMA_I2C3_SDA IMX8QXP_ENET0_MDIO 1 342*4882a593Smuzhiyun #define IMX8QXP_ENET0_MDIO_CONN_ENET1_MDIO IMX8QXP_ENET0_MDIO 2 343*4882a593Smuzhiyun #define IMX8QXP_ENET0_MDIO_LSIO_GPIO5_IO10 IMX8QXP_ENET0_MDIO 4 344*4882a593Smuzhiyun #define IMX8QXP_ENET0_MDC_CONN_ENET0_MDC IMX8QXP_ENET0_MDC 0 345*4882a593Smuzhiyun #define IMX8QXP_ENET0_MDC_ADMA_I2C3_SCL IMX8QXP_ENET0_MDC 1 346*4882a593Smuzhiyun #define IMX8QXP_ENET0_MDC_CONN_ENET1_MDC IMX8QXP_ENET0_MDC 2 347*4882a593Smuzhiyun #define IMX8QXP_ENET0_MDC_LSIO_GPIO5_IO11 IMX8QXP_ENET0_MDC 4 348*4882a593Smuzhiyun #define IMX8QXP_ESAI0_FSR_ADMA_ESAI0_FSR IMX8QXP_ESAI0_FSR 0 349*4882a593Smuzhiyun #define IMX8QXP_ESAI0_FSR_CONN_ENET1_RCLK50M_OUT IMX8QXP_ESAI0_FSR 1 350*4882a593Smuzhiyun #define IMX8QXP_ESAI0_FSR_ADMA_LCDIF_D00 IMX8QXP_ESAI0_FSR 2 351*4882a593Smuzhiyun #define IMX8QXP_ESAI0_FSR_CONN_ENET1_RGMII_TXC IMX8QXP_ESAI0_FSR 3 352*4882a593Smuzhiyun #define IMX8QXP_ESAI0_FSR_CONN_ENET1_RCLK50M_IN IMX8QXP_ESAI0_FSR 4 353*4882a593Smuzhiyun #define IMX8QXP_ESAI0_FST_ADMA_ESAI0_FST IMX8QXP_ESAI0_FST 0 354*4882a593Smuzhiyun #define IMX8QXP_ESAI0_FST_CONN_MLB_CLK IMX8QXP_ESAI0_FST 1 355*4882a593Smuzhiyun #define IMX8QXP_ESAI0_FST_ADMA_LCDIF_D01 IMX8QXP_ESAI0_FST 2 356*4882a593Smuzhiyun #define IMX8QXP_ESAI0_FST_CONN_ENET1_RGMII_TXD2 IMX8QXP_ESAI0_FST 3 357*4882a593Smuzhiyun #define IMX8QXP_ESAI0_FST_LSIO_GPIO0_IO01 IMX8QXP_ESAI0_FST 4 358*4882a593Smuzhiyun #define IMX8QXP_ESAI0_SCKR_ADMA_ESAI0_SCKR IMX8QXP_ESAI0_SCKR 0 359*4882a593Smuzhiyun #define IMX8QXP_ESAI0_SCKR_ADMA_LCDIF_D02 IMX8QXP_ESAI0_SCKR 2 360*4882a593Smuzhiyun #define IMX8QXP_ESAI0_SCKR_CONN_ENET1_RGMII_TX_CTL IMX8QXP_ESAI0_SCKR 3 361*4882a593Smuzhiyun #define IMX8QXP_ESAI0_SCKR_LSIO_GPIO0_IO02 IMX8QXP_ESAI0_SCKR 4 362*4882a593Smuzhiyun #define IMX8QXP_ESAI0_SCKT_ADMA_ESAI0_SCKT IMX8QXP_ESAI0_SCKT 0 363*4882a593Smuzhiyun #define IMX8QXP_ESAI0_SCKT_CONN_MLB_SIG IMX8QXP_ESAI0_SCKT 1 364*4882a593Smuzhiyun #define IMX8QXP_ESAI0_SCKT_ADMA_LCDIF_D03 IMX8QXP_ESAI0_SCKT 2 365*4882a593Smuzhiyun #define IMX8QXP_ESAI0_SCKT_CONN_ENET1_RGMII_TXD3 IMX8QXP_ESAI0_SCKT 3 366*4882a593Smuzhiyun #define IMX8QXP_ESAI0_SCKT_LSIO_GPIO0_IO03 IMX8QXP_ESAI0_SCKT 4 367*4882a593Smuzhiyun #define IMX8QXP_ESAI0_TX0_ADMA_ESAI0_TX0 IMX8QXP_ESAI0_TX0 0 368*4882a593Smuzhiyun #define IMX8QXP_ESAI0_TX0_CONN_MLB_DATA IMX8QXP_ESAI0_TX0 1 369*4882a593Smuzhiyun #define IMX8QXP_ESAI0_TX0_ADMA_LCDIF_D04 IMX8QXP_ESAI0_TX0 2 370*4882a593Smuzhiyun #define IMX8QXP_ESAI0_TX0_CONN_ENET1_RGMII_RXC IMX8QXP_ESAI0_TX0 3 371*4882a593Smuzhiyun #define IMX8QXP_ESAI0_TX0_LSIO_GPIO0_IO04 IMX8QXP_ESAI0_TX0 4 372*4882a593Smuzhiyun #define IMX8QXP_ESAI0_TX1_ADMA_ESAI0_TX1 IMX8QXP_ESAI0_TX1 0 373*4882a593Smuzhiyun #define IMX8QXP_ESAI0_TX1_ADMA_LCDIF_D05 IMX8QXP_ESAI0_TX1 2 374*4882a593Smuzhiyun #define IMX8QXP_ESAI0_TX1_CONN_ENET1_RGMII_RXD3 IMX8QXP_ESAI0_TX1 3 375*4882a593Smuzhiyun #define IMX8QXP_ESAI0_TX1_LSIO_GPIO0_IO05 IMX8QXP_ESAI0_TX1 4 376*4882a593Smuzhiyun #define IMX8QXP_ESAI0_TX2_RX3_ADMA_ESAI0_TX2_RX3 IMX8QXP_ESAI0_TX2_RX3 0 377*4882a593Smuzhiyun #define IMX8QXP_ESAI0_TX2_RX3_CONN_ENET1_RMII_RX_ER IMX8QXP_ESAI0_TX2_RX3 1 378*4882a593Smuzhiyun #define IMX8QXP_ESAI0_TX2_RX3_ADMA_LCDIF_D06 IMX8QXP_ESAI0_TX2_RX3 2 379*4882a593Smuzhiyun #define IMX8QXP_ESAI0_TX2_RX3_CONN_ENET1_RGMII_RXD2 IMX8QXP_ESAI0_TX2_RX3 3 380*4882a593Smuzhiyun #define IMX8QXP_ESAI0_TX2_RX3_LSIO_GPIO0_IO06 IMX8QXP_ESAI0_TX2_RX3 4 381*4882a593Smuzhiyun #define IMX8QXP_ESAI0_TX3_RX2_ADMA_ESAI0_TX3_RX2 IMX8QXP_ESAI0_TX3_RX2 0 382*4882a593Smuzhiyun #define IMX8QXP_ESAI0_TX3_RX2_ADMA_LCDIF_D07 IMX8QXP_ESAI0_TX3_RX2 2 383*4882a593Smuzhiyun #define IMX8QXP_ESAI0_TX3_RX2_CONN_ENET1_RGMII_RXD1 IMX8QXP_ESAI0_TX3_RX2 3 384*4882a593Smuzhiyun #define IMX8QXP_ESAI0_TX3_RX2_LSIO_GPIO0_IO07 IMX8QXP_ESAI0_TX3_RX2 4 385*4882a593Smuzhiyun #define IMX8QXP_ESAI0_TX4_RX1_ADMA_ESAI0_TX4_RX1 IMX8QXP_ESAI0_TX4_RX1 0 386*4882a593Smuzhiyun #define IMX8QXP_ESAI0_TX4_RX1_ADMA_LCDIF_D08 IMX8QXP_ESAI0_TX4_RX1 2 387*4882a593Smuzhiyun #define IMX8QXP_ESAI0_TX4_RX1_CONN_ENET1_RGMII_TXD0 IMX8QXP_ESAI0_TX4_RX1 3 388*4882a593Smuzhiyun #define IMX8QXP_ESAI0_TX4_RX1_LSIO_GPIO0_IO08 IMX8QXP_ESAI0_TX4_RX1 4 389*4882a593Smuzhiyun #define IMX8QXP_ESAI0_TX5_RX0_ADMA_ESAI0_TX5_RX0 IMX8QXP_ESAI0_TX5_RX0 0 390*4882a593Smuzhiyun #define IMX8QXP_ESAI0_TX5_RX0_ADMA_LCDIF_D09 IMX8QXP_ESAI0_TX5_RX0 2 391*4882a593Smuzhiyun #define IMX8QXP_ESAI0_TX5_RX0_CONN_ENET1_RGMII_TXD1 IMX8QXP_ESAI0_TX5_RX0 3 392*4882a593Smuzhiyun #define IMX8QXP_ESAI0_TX5_RX0_LSIO_GPIO0_IO09 IMX8QXP_ESAI0_TX5_RX0 4 393*4882a593Smuzhiyun #define IMX8QXP_SPDIF0_RX_ADMA_SPDIF0_RX IMX8QXP_SPDIF0_RX 0 394*4882a593Smuzhiyun #define IMX8QXP_SPDIF0_RX_ADMA_MQS_R IMX8QXP_SPDIF0_RX 1 395*4882a593Smuzhiyun #define IMX8QXP_SPDIF0_RX_ADMA_LCDIF_D10 IMX8QXP_SPDIF0_RX 2 396*4882a593Smuzhiyun #define IMX8QXP_SPDIF0_RX_CONN_ENET1_RGMII_RXD0 IMX8QXP_SPDIF0_RX 3 397*4882a593Smuzhiyun #define IMX8QXP_SPDIF0_RX_LSIO_GPIO0_IO10 IMX8QXP_SPDIF0_RX 4 398*4882a593Smuzhiyun #define IMX8QXP_SPDIF0_TX_ADMA_SPDIF0_TX IMX8QXP_SPDIF0_TX 0 399*4882a593Smuzhiyun #define IMX8QXP_SPDIF0_TX_ADMA_MQS_L IMX8QXP_SPDIF0_TX 1 400*4882a593Smuzhiyun #define IMX8QXP_SPDIF0_TX_ADMA_LCDIF_D11 IMX8QXP_SPDIF0_TX 2 401*4882a593Smuzhiyun #define IMX8QXP_SPDIF0_TX_CONN_ENET1_RGMII_RX_CTL IMX8QXP_SPDIF0_TX 3 402*4882a593Smuzhiyun #define IMX8QXP_SPDIF0_TX_LSIO_GPIO0_IO11 IMX8QXP_SPDIF0_TX 4 403*4882a593Smuzhiyun #define IMX8QXP_SPDIF0_EXT_CLK_ADMA_SPDIF0_EXT_CLK IMX8QXP_SPDIF0_EXT_CLK 0 404*4882a593Smuzhiyun #define IMX8QXP_SPDIF0_EXT_CLK_ADMA_LCDIF_D12 IMX8QXP_SPDIF0_EXT_CLK 2 405*4882a593Smuzhiyun #define IMX8QXP_SPDIF0_EXT_CLK_CONN_ENET1_REFCLK_125M_25M IMX8QXP_SPDIF0_EXT_CLK 3 406*4882a593Smuzhiyun #define IMX8QXP_SPDIF0_EXT_CLK_LSIO_GPIO0_IO12 IMX8QXP_SPDIF0_EXT_CLK 4 407*4882a593Smuzhiyun #define IMX8QXP_SPI3_SCK_ADMA_SPI3_SCK IMX8QXP_SPI3_SCK 0 408*4882a593Smuzhiyun #define IMX8QXP_SPI3_SCK_ADMA_LCDIF_D13 IMX8QXP_SPI3_SCK 2 409*4882a593Smuzhiyun #define IMX8QXP_SPI3_SCK_LSIO_GPIO0_IO13 IMX8QXP_SPI3_SCK 4 410*4882a593Smuzhiyun #define IMX8QXP_SPI3_SDO_ADMA_SPI3_SDO IMX8QXP_SPI3_SDO 0 411*4882a593Smuzhiyun #define IMX8QXP_SPI3_SDO_ADMA_LCDIF_D14 IMX8QXP_SPI3_SDO 2 412*4882a593Smuzhiyun #define IMX8QXP_SPI3_SDO_LSIO_GPIO0_IO14 IMX8QXP_SPI3_SDO 4 413*4882a593Smuzhiyun #define IMX8QXP_SPI3_SDI_ADMA_SPI3_SDI IMX8QXP_SPI3_SDI 0 414*4882a593Smuzhiyun #define IMX8QXP_SPI3_SDI_ADMA_LCDIF_D15 IMX8QXP_SPI3_SDI 2 415*4882a593Smuzhiyun #define IMX8QXP_SPI3_SDI_LSIO_GPIO0_IO15 IMX8QXP_SPI3_SDI 4 416*4882a593Smuzhiyun #define IMX8QXP_SPI3_CS0_ADMA_SPI3_CS0 IMX8QXP_SPI3_CS0 0 417*4882a593Smuzhiyun #define IMX8QXP_SPI3_CS0_ADMA_ACM_MCLK_OUT1 IMX8QXP_SPI3_CS0 1 418*4882a593Smuzhiyun #define IMX8QXP_SPI3_CS0_ADMA_LCDIF_HSYNC IMX8QXP_SPI3_CS0 2 419*4882a593Smuzhiyun #define IMX8QXP_SPI3_CS0_LSIO_GPIO0_IO16 IMX8QXP_SPI3_CS0 4 420*4882a593Smuzhiyun #define IMX8QXP_SPI3_CS1_ADMA_SPI3_CS1 IMX8QXP_SPI3_CS1 0 421*4882a593Smuzhiyun #define IMX8QXP_SPI3_CS1_ADMA_I2C3_SCL IMX8QXP_SPI3_CS1 1 422*4882a593Smuzhiyun #define IMX8QXP_SPI3_CS1_ADMA_LCDIF_RESET IMX8QXP_SPI3_CS1 2 423*4882a593Smuzhiyun #define IMX8QXP_SPI3_CS1_ADMA_SPI2_CS0 IMX8QXP_SPI3_CS1 3 424*4882a593Smuzhiyun #define IMX8QXP_SPI3_CS1_ADMA_LCDIF_D16 IMX8QXP_SPI3_CS1 4 425*4882a593Smuzhiyun #define IMX8QXP_MCLK_IN1_ADMA_ACM_MCLK_IN1 IMX8QXP_MCLK_IN1 0 426*4882a593Smuzhiyun #define IMX8QXP_MCLK_IN1_ADMA_I2C3_SDA IMX8QXP_MCLK_IN1 1 427*4882a593Smuzhiyun #define IMX8QXP_MCLK_IN1_ADMA_LCDIF_EN IMX8QXP_MCLK_IN1 2 428*4882a593Smuzhiyun #define IMX8QXP_MCLK_IN1_ADMA_SPI2_SCK IMX8QXP_MCLK_IN1 3 429*4882a593Smuzhiyun #define IMX8QXP_MCLK_IN1_ADMA_LCDIF_D17 IMX8QXP_MCLK_IN1 4 430*4882a593Smuzhiyun #define IMX8QXP_MCLK_IN0_ADMA_ACM_MCLK_IN0 IMX8QXP_MCLK_IN0 0 431*4882a593Smuzhiyun #define IMX8QXP_MCLK_IN0_ADMA_ESAI0_RX_HF_CLK IMX8QXP_MCLK_IN0 1 432*4882a593Smuzhiyun #define IMX8QXP_MCLK_IN0_ADMA_LCDIF_VSYNC IMX8QXP_MCLK_IN0 2 433*4882a593Smuzhiyun #define IMX8QXP_MCLK_IN0_ADMA_SPI2_SDI IMX8QXP_MCLK_IN0 3 434*4882a593Smuzhiyun #define IMX8QXP_MCLK_IN0_LSIO_GPIO0_IO19 IMX8QXP_MCLK_IN0 4 435*4882a593Smuzhiyun #define IMX8QXP_MCLK_OUT0_ADMA_ACM_MCLK_OUT0 IMX8QXP_MCLK_OUT0 0 436*4882a593Smuzhiyun #define IMX8QXP_MCLK_OUT0_ADMA_ESAI0_TX_HF_CLK IMX8QXP_MCLK_OUT0 1 437*4882a593Smuzhiyun #define IMX8QXP_MCLK_OUT0_ADMA_LCDIF_CLK IMX8QXP_MCLK_OUT0 2 438*4882a593Smuzhiyun #define IMX8QXP_MCLK_OUT0_ADMA_SPI2_SDO IMX8QXP_MCLK_OUT0 3 439*4882a593Smuzhiyun #define IMX8QXP_MCLK_OUT0_LSIO_GPIO0_IO20 IMX8QXP_MCLK_OUT0 4 440*4882a593Smuzhiyun #define IMX8QXP_UART1_TX_ADMA_UART1_TX IMX8QXP_UART1_TX 0 441*4882a593Smuzhiyun #define IMX8QXP_UART1_TX_LSIO_PWM0_OUT IMX8QXP_UART1_TX 1 442*4882a593Smuzhiyun #define IMX8QXP_UART1_TX_LSIO_GPT0_CAPTURE IMX8QXP_UART1_TX 2 443*4882a593Smuzhiyun #define IMX8QXP_UART1_TX_LSIO_GPIO0_IO21 IMX8QXP_UART1_TX 4 444*4882a593Smuzhiyun #define IMX8QXP_UART1_RX_ADMA_UART1_RX IMX8QXP_UART1_RX 0 445*4882a593Smuzhiyun #define IMX8QXP_UART1_RX_LSIO_PWM1_OUT IMX8QXP_UART1_RX 1 446*4882a593Smuzhiyun #define IMX8QXP_UART1_RX_LSIO_GPT0_COMPARE IMX8QXP_UART1_RX 2 447*4882a593Smuzhiyun #define IMX8QXP_UART1_RX_LSIO_GPT1_CLK IMX8QXP_UART1_RX 3 448*4882a593Smuzhiyun #define IMX8QXP_UART1_RX_LSIO_GPIO0_IO22 IMX8QXP_UART1_RX 4 449*4882a593Smuzhiyun #define IMX8QXP_UART1_RTS_B_ADMA_UART1_RTS_B IMX8QXP_UART1_RTS_B 0 450*4882a593Smuzhiyun #define IMX8QXP_UART1_RTS_B_LSIO_PWM2_OUT IMX8QXP_UART1_RTS_B 1 451*4882a593Smuzhiyun #define IMX8QXP_UART1_RTS_B_ADMA_LCDIF_D16 IMX8QXP_UART1_RTS_B 2 452*4882a593Smuzhiyun #define IMX8QXP_UART1_RTS_B_LSIO_GPT1_CAPTURE IMX8QXP_UART1_RTS_B 3 453*4882a593Smuzhiyun #define IMX8QXP_UART1_RTS_B_LSIO_GPT0_CLK IMX8QXP_UART1_RTS_B 4 454*4882a593Smuzhiyun #define IMX8QXP_UART1_CTS_B_ADMA_UART1_CTS_B IMX8QXP_UART1_CTS_B 0 455*4882a593Smuzhiyun #define IMX8QXP_UART1_CTS_B_LSIO_PWM3_OUT IMX8QXP_UART1_CTS_B 1 456*4882a593Smuzhiyun #define IMX8QXP_UART1_CTS_B_ADMA_LCDIF_D17 IMX8QXP_UART1_CTS_B 2 457*4882a593Smuzhiyun #define IMX8QXP_UART1_CTS_B_LSIO_GPT1_COMPARE IMX8QXP_UART1_CTS_B 3 458*4882a593Smuzhiyun #define IMX8QXP_UART1_CTS_B_LSIO_GPIO0_IO24 IMX8QXP_UART1_CTS_B 4 459*4882a593Smuzhiyun #define IMX8QXP_SAI0_TXD_ADMA_SAI0_TXD IMX8QXP_SAI0_TXD 0 460*4882a593Smuzhiyun #define IMX8QXP_SAI0_TXD_ADMA_SAI1_RXC IMX8QXP_SAI0_TXD 1 461*4882a593Smuzhiyun #define IMX8QXP_SAI0_TXD_ADMA_SPI1_SDO IMX8QXP_SAI0_TXD 2 462*4882a593Smuzhiyun #define IMX8QXP_SAI0_TXD_ADMA_LCDIF_D18 IMX8QXP_SAI0_TXD 3 463*4882a593Smuzhiyun #define IMX8QXP_SAI0_TXD_LSIO_GPIO0_IO25 IMX8QXP_SAI0_TXD 4 464*4882a593Smuzhiyun #define IMX8QXP_SAI0_TXC_ADMA_SAI0_TXC IMX8QXP_SAI0_TXC 0 465*4882a593Smuzhiyun #define IMX8QXP_SAI0_TXC_ADMA_SAI1_TXD IMX8QXP_SAI0_TXC 1 466*4882a593Smuzhiyun #define IMX8QXP_SAI0_TXC_ADMA_SPI1_SDI IMX8QXP_SAI0_TXC 2 467*4882a593Smuzhiyun #define IMX8QXP_SAI0_TXC_ADMA_LCDIF_D19 IMX8QXP_SAI0_TXC 3 468*4882a593Smuzhiyun #define IMX8QXP_SAI0_TXC_LSIO_GPIO0_IO26 IMX8QXP_SAI0_TXC 4 469*4882a593Smuzhiyun #define IMX8QXP_SAI0_RXD_ADMA_SAI0_RXD IMX8QXP_SAI0_RXD 0 470*4882a593Smuzhiyun #define IMX8QXP_SAI0_RXD_ADMA_SAI1_RXFS IMX8QXP_SAI0_RXD 1 471*4882a593Smuzhiyun #define IMX8QXP_SAI0_RXD_ADMA_SPI1_CS0 IMX8QXP_SAI0_RXD 2 472*4882a593Smuzhiyun #define IMX8QXP_SAI0_RXD_ADMA_LCDIF_D20 IMX8QXP_SAI0_RXD 3 473*4882a593Smuzhiyun #define IMX8QXP_SAI0_RXD_LSIO_GPIO0_IO27 IMX8QXP_SAI0_RXD 4 474*4882a593Smuzhiyun #define IMX8QXP_SAI0_TXFS_ADMA_SAI0_TXFS IMX8QXP_SAI0_TXFS 0 475*4882a593Smuzhiyun #define IMX8QXP_SAI0_TXFS_ADMA_SPI2_CS1 IMX8QXP_SAI0_TXFS 1 476*4882a593Smuzhiyun #define IMX8QXP_SAI0_TXFS_ADMA_SPI1_SCK IMX8QXP_SAI0_TXFS 2 477*4882a593Smuzhiyun #define IMX8QXP_SAI0_TXFS_LSIO_GPIO0_IO28 IMX8QXP_SAI0_TXFS 4 478*4882a593Smuzhiyun #define IMX8QXP_SAI1_RXD_ADMA_SAI1_RXD IMX8QXP_SAI1_RXD 0 479*4882a593Smuzhiyun #define IMX8QXP_SAI1_RXD_ADMA_SAI0_RXFS IMX8QXP_SAI1_RXD 1 480*4882a593Smuzhiyun #define IMX8QXP_SAI1_RXD_ADMA_SPI1_CS1 IMX8QXP_SAI1_RXD 2 481*4882a593Smuzhiyun #define IMX8QXP_SAI1_RXD_ADMA_LCDIF_D21 IMX8QXP_SAI1_RXD 3 482*4882a593Smuzhiyun #define IMX8QXP_SAI1_RXD_LSIO_GPIO0_IO29 IMX8QXP_SAI1_RXD 4 483*4882a593Smuzhiyun #define IMX8QXP_SAI1_RXC_ADMA_SAI1_RXC IMX8QXP_SAI1_RXC 0 484*4882a593Smuzhiyun #define IMX8QXP_SAI1_RXC_ADMA_SAI1_TXC IMX8QXP_SAI1_RXC 1 485*4882a593Smuzhiyun #define IMX8QXP_SAI1_RXC_ADMA_LCDIF_D22 IMX8QXP_SAI1_RXC 3 486*4882a593Smuzhiyun #define IMX8QXP_SAI1_RXC_LSIO_GPIO0_IO30 IMX8QXP_SAI1_RXC 4 487*4882a593Smuzhiyun #define IMX8QXP_SAI1_RXFS_ADMA_SAI1_RXFS IMX8QXP_SAI1_RXFS 0 488*4882a593Smuzhiyun #define IMX8QXP_SAI1_RXFS_ADMA_SAI1_TXFS IMX8QXP_SAI1_RXFS 1 489*4882a593Smuzhiyun #define IMX8QXP_SAI1_RXFS_ADMA_LCDIF_D23 IMX8QXP_SAI1_RXFS 3 490*4882a593Smuzhiyun #define IMX8QXP_SAI1_RXFS_LSIO_GPIO0_IO31 IMX8QXP_SAI1_RXFS 4 491*4882a593Smuzhiyun #define IMX8QXP_SPI2_CS0_ADMA_SPI2_CS0 IMX8QXP_SPI2_CS0 0 492*4882a593Smuzhiyun #define IMX8QXP_SPI2_CS0_LSIO_GPIO1_IO00 IMX8QXP_SPI2_CS0 4 493*4882a593Smuzhiyun #define IMX8QXP_SPI2_SDO_ADMA_SPI2_SDO IMX8QXP_SPI2_SDO 0 494*4882a593Smuzhiyun #define IMX8QXP_SPI2_SDO_LSIO_GPIO1_IO01 IMX8QXP_SPI2_SDO 4 495*4882a593Smuzhiyun #define IMX8QXP_SPI2_SDI_ADMA_SPI2_SDI IMX8QXP_SPI2_SDI 0 496*4882a593Smuzhiyun #define IMX8QXP_SPI2_SDI_LSIO_GPIO1_IO02 IMX8QXP_SPI2_SDI 4 497*4882a593Smuzhiyun #define IMX8QXP_SPI2_SCK_ADMA_SPI2_SCK IMX8QXP_SPI2_SCK 0 498*4882a593Smuzhiyun #define IMX8QXP_SPI2_SCK_LSIO_GPIO1_IO03 IMX8QXP_SPI2_SCK 4 499*4882a593Smuzhiyun #define IMX8QXP_SPI0_SCK_ADMA_SPI0_SCK IMX8QXP_SPI0_SCK 0 500*4882a593Smuzhiyun #define IMX8QXP_SPI0_SCK_ADMA_SAI0_TXC IMX8QXP_SPI0_SCK 1 501*4882a593Smuzhiyun #define IMX8QXP_SPI0_SCK_M40_I2C0_SCL IMX8QXP_SPI0_SCK 2 502*4882a593Smuzhiyun #define IMX8QXP_SPI0_SCK_M40_GPIO0_IO00 IMX8QXP_SPI0_SCK 3 503*4882a593Smuzhiyun #define IMX8QXP_SPI0_SCK_LSIO_GPIO1_IO04 IMX8QXP_SPI0_SCK 4 504*4882a593Smuzhiyun #define IMX8QXP_SPI0_SDI_ADMA_SPI0_SDI IMX8QXP_SPI0_SDI 0 505*4882a593Smuzhiyun #define IMX8QXP_SPI0_SDI_ADMA_SAI0_TXD IMX8QXP_SPI0_SDI 1 506*4882a593Smuzhiyun #define IMX8QXP_SPI0_SDI_M40_TPM0_CH0 IMX8QXP_SPI0_SDI 2 507*4882a593Smuzhiyun #define IMX8QXP_SPI0_SDI_M40_GPIO0_IO02 IMX8QXP_SPI0_SDI 3 508*4882a593Smuzhiyun #define IMX8QXP_SPI0_SDI_LSIO_GPIO1_IO05 IMX8QXP_SPI0_SDI 4 509*4882a593Smuzhiyun #define IMX8QXP_SPI0_SDO_ADMA_SPI0_SDO IMX8QXP_SPI0_SDO 0 510*4882a593Smuzhiyun #define IMX8QXP_SPI0_SDO_ADMA_SAI0_TXFS IMX8QXP_SPI0_SDO 1 511*4882a593Smuzhiyun #define IMX8QXP_SPI0_SDO_M40_I2C0_SDA IMX8QXP_SPI0_SDO 2 512*4882a593Smuzhiyun #define IMX8QXP_SPI0_SDO_M40_GPIO0_IO01 IMX8QXP_SPI0_SDO 3 513*4882a593Smuzhiyun #define IMX8QXP_SPI0_SDO_LSIO_GPIO1_IO06 IMX8QXP_SPI0_SDO 4 514*4882a593Smuzhiyun #define IMX8QXP_SPI0_CS1_ADMA_SPI0_CS1 IMX8QXP_SPI0_CS1 0 515*4882a593Smuzhiyun #define IMX8QXP_SPI0_CS1_ADMA_SAI0_RXC IMX8QXP_SPI0_CS1 1 516*4882a593Smuzhiyun #define IMX8QXP_SPI0_CS1_ADMA_SAI1_TXD IMX8QXP_SPI0_CS1 2 517*4882a593Smuzhiyun #define IMX8QXP_SPI0_CS1_ADMA_LCD_PWM0_OUT IMX8QXP_SPI0_CS1 3 518*4882a593Smuzhiyun #define IMX8QXP_SPI0_CS1_LSIO_GPIO1_IO07 IMX8QXP_SPI0_CS1 4 519*4882a593Smuzhiyun #define IMX8QXP_SPI0_CS0_ADMA_SPI0_CS0 IMX8QXP_SPI0_CS0 0 520*4882a593Smuzhiyun #define IMX8QXP_SPI0_CS0_ADMA_SAI0_RXD IMX8QXP_SPI0_CS0 1 521*4882a593Smuzhiyun #define IMX8QXP_SPI0_CS0_M40_TPM0_CH1 IMX8QXP_SPI0_CS0 2 522*4882a593Smuzhiyun #define IMX8QXP_SPI0_CS0_M40_GPIO0_IO03 IMX8QXP_SPI0_CS0 3 523*4882a593Smuzhiyun #define IMX8QXP_SPI0_CS0_LSIO_GPIO1_IO08 IMX8QXP_SPI0_CS0 4 524*4882a593Smuzhiyun #define IMX8QXP_ADC_IN1_ADMA_ADC_IN1 IMX8QXP_ADC_IN1 0 525*4882a593Smuzhiyun #define IMX8QXP_ADC_IN1_M40_I2C0_SDA IMX8QXP_ADC_IN1 1 526*4882a593Smuzhiyun #define IMX8QXP_ADC_IN1_M40_GPIO0_IO01 IMX8QXP_ADC_IN1 2 527*4882a593Smuzhiyun #define IMX8QXP_ADC_IN1_LSIO_GPIO1_IO09 IMX8QXP_ADC_IN1 4 528*4882a593Smuzhiyun #define IMX8QXP_ADC_IN0_ADMA_ADC_IN0 IMX8QXP_ADC_IN0 0 529*4882a593Smuzhiyun #define IMX8QXP_ADC_IN0_M40_I2C0_SCL IMX8QXP_ADC_IN0 1 530*4882a593Smuzhiyun #define IMX8QXP_ADC_IN0_M40_GPIO0_IO00 IMX8QXP_ADC_IN0 2 531*4882a593Smuzhiyun #define IMX8QXP_ADC_IN0_LSIO_GPIO1_IO10 IMX8QXP_ADC_IN0 4 532*4882a593Smuzhiyun #define IMX8QXP_ADC_IN3_ADMA_ADC_IN3 IMX8QXP_ADC_IN3 0 533*4882a593Smuzhiyun #define IMX8QXP_ADC_IN3_M40_UART0_TX IMX8QXP_ADC_IN3 1 534*4882a593Smuzhiyun #define IMX8QXP_ADC_IN3_M40_GPIO0_IO03 IMX8QXP_ADC_IN3 2 535*4882a593Smuzhiyun #define IMX8QXP_ADC_IN3_ADMA_ACM_MCLK_OUT0 IMX8QXP_ADC_IN3 3 536*4882a593Smuzhiyun #define IMX8QXP_ADC_IN3_LSIO_GPIO1_IO11 IMX8QXP_ADC_IN3 4 537*4882a593Smuzhiyun #define IMX8QXP_ADC_IN2_ADMA_ADC_IN2 IMX8QXP_ADC_IN2 0 538*4882a593Smuzhiyun #define IMX8QXP_ADC_IN2_M40_UART0_RX IMX8QXP_ADC_IN2 1 539*4882a593Smuzhiyun #define IMX8QXP_ADC_IN2_M40_GPIO0_IO02 IMX8QXP_ADC_IN2 2 540*4882a593Smuzhiyun #define IMX8QXP_ADC_IN2_ADMA_ACM_MCLK_IN0 IMX8QXP_ADC_IN2 3 541*4882a593Smuzhiyun #define IMX8QXP_ADC_IN2_LSIO_GPIO1_IO12 IMX8QXP_ADC_IN2 4 542*4882a593Smuzhiyun #define IMX8QXP_ADC_IN5_ADMA_ADC_IN5 IMX8QXP_ADC_IN5 0 543*4882a593Smuzhiyun #define IMX8QXP_ADC_IN5_M40_TPM0_CH1 IMX8QXP_ADC_IN5 1 544*4882a593Smuzhiyun #define IMX8QXP_ADC_IN5_M40_GPIO0_IO05 IMX8QXP_ADC_IN5 2 545*4882a593Smuzhiyun #define IMX8QXP_ADC_IN5_LSIO_GPIO1_IO13 IMX8QXP_ADC_IN5 4 546*4882a593Smuzhiyun #define IMX8QXP_ADC_IN4_ADMA_ADC_IN4 IMX8QXP_ADC_IN4 0 547*4882a593Smuzhiyun #define IMX8QXP_ADC_IN4_M40_TPM0_CH0 IMX8QXP_ADC_IN4 1 548*4882a593Smuzhiyun #define IMX8QXP_ADC_IN4_M40_GPIO0_IO04 IMX8QXP_ADC_IN4 2 549*4882a593Smuzhiyun #define IMX8QXP_ADC_IN4_LSIO_GPIO1_IO14 IMX8QXP_ADC_IN4 4 550*4882a593Smuzhiyun #define IMX8QXP_FLEXCAN0_RX_ADMA_FLEXCAN0_RX IMX8QXP_FLEXCAN0_RX 0 551*4882a593Smuzhiyun #define IMX8QXP_FLEXCAN0_RX_ADMA_SAI2_RXC IMX8QXP_FLEXCAN0_RX 1 552*4882a593Smuzhiyun #define IMX8QXP_FLEXCAN0_RX_ADMA_UART0_RTS_B IMX8QXP_FLEXCAN0_RX 2 553*4882a593Smuzhiyun #define IMX8QXP_FLEXCAN0_RX_ADMA_SAI1_TXC IMX8QXP_FLEXCAN0_RX 3 554*4882a593Smuzhiyun #define IMX8QXP_FLEXCAN0_RX_LSIO_GPIO1_IO15 IMX8QXP_FLEXCAN0_RX 4 555*4882a593Smuzhiyun #define IMX8QXP_FLEXCAN0_TX_ADMA_FLEXCAN0_TX IMX8QXP_FLEXCAN0_TX 0 556*4882a593Smuzhiyun #define IMX8QXP_FLEXCAN0_TX_ADMA_SAI2_RXD IMX8QXP_FLEXCAN0_TX 1 557*4882a593Smuzhiyun #define IMX8QXP_FLEXCAN0_TX_ADMA_UART0_CTS_B IMX8QXP_FLEXCAN0_TX 2 558*4882a593Smuzhiyun #define IMX8QXP_FLEXCAN0_TX_ADMA_SAI1_TXFS IMX8QXP_FLEXCAN0_TX 3 559*4882a593Smuzhiyun #define IMX8QXP_FLEXCAN0_TX_LSIO_GPIO1_IO16 IMX8QXP_FLEXCAN0_TX 4 560*4882a593Smuzhiyun #define IMX8QXP_FLEXCAN1_RX_ADMA_FLEXCAN1_RX IMX8QXP_FLEXCAN1_RX 0 561*4882a593Smuzhiyun #define IMX8QXP_FLEXCAN1_RX_ADMA_SAI2_RXFS IMX8QXP_FLEXCAN1_RX 1 562*4882a593Smuzhiyun #define IMX8QXP_FLEXCAN1_RX_ADMA_FTM_CH2 IMX8QXP_FLEXCAN1_RX 2 563*4882a593Smuzhiyun #define IMX8QXP_FLEXCAN1_RX_ADMA_SAI1_TXD IMX8QXP_FLEXCAN1_RX 3 564*4882a593Smuzhiyun #define IMX8QXP_FLEXCAN1_RX_LSIO_GPIO1_IO17 IMX8QXP_FLEXCAN1_RX 4 565*4882a593Smuzhiyun #define IMX8QXP_FLEXCAN1_TX_ADMA_FLEXCAN1_TX IMX8QXP_FLEXCAN1_TX 0 566*4882a593Smuzhiyun #define IMX8QXP_FLEXCAN1_TX_ADMA_SAI3_RXC IMX8QXP_FLEXCAN1_TX 1 567*4882a593Smuzhiyun #define IMX8QXP_FLEXCAN1_TX_ADMA_DMA0_REQ_IN0 IMX8QXP_FLEXCAN1_TX 2 568*4882a593Smuzhiyun #define IMX8QXP_FLEXCAN1_TX_ADMA_SAI1_RXD IMX8QXP_FLEXCAN1_TX 3 569*4882a593Smuzhiyun #define IMX8QXP_FLEXCAN1_TX_LSIO_GPIO1_IO18 IMX8QXP_FLEXCAN1_TX 4 570*4882a593Smuzhiyun #define IMX8QXP_FLEXCAN2_RX_ADMA_FLEXCAN2_RX IMX8QXP_FLEXCAN2_RX 0 571*4882a593Smuzhiyun #define IMX8QXP_FLEXCAN2_RX_ADMA_SAI3_RXD IMX8QXP_FLEXCAN2_RX 1 572*4882a593Smuzhiyun #define IMX8QXP_FLEXCAN2_RX_ADMA_UART3_RX IMX8QXP_FLEXCAN2_RX 2 573*4882a593Smuzhiyun #define IMX8QXP_FLEXCAN2_RX_ADMA_SAI1_RXFS IMX8QXP_FLEXCAN2_RX 3 574*4882a593Smuzhiyun #define IMX8QXP_FLEXCAN2_RX_LSIO_GPIO1_IO19 IMX8QXP_FLEXCAN2_RX 4 575*4882a593Smuzhiyun #define IMX8QXP_FLEXCAN2_TX_ADMA_FLEXCAN2_TX IMX8QXP_FLEXCAN2_TX 0 576*4882a593Smuzhiyun #define IMX8QXP_FLEXCAN2_TX_ADMA_SAI3_RXFS IMX8QXP_FLEXCAN2_TX 1 577*4882a593Smuzhiyun #define IMX8QXP_FLEXCAN2_TX_ADMA_UART3_TX IMX8QXP_FLEXCAN2_TX 2 578*4882a593Smuzhiyun #define IMX8QXP_FLEXCAN2_TX_ADMA_SAI1_RXC IMX8QXP_FLEXCAN2_TX 3 579*4882a593Smuzhiyun #define IMX8QXP_FLEXCAN2_TX_LSIO_GPIO1_IO20 IMX8QXP_FLEXCAN2_TX 4 580*4882a593Smuzhiyun #define IMX8QXP_UART0_RX_ADMA_UART0_RX IMX8QXP_UART0_RX 0 581*4882a593Smuzhiyun #define IMX8QXP_UART0_RX_ADMA_MQS_R IMX8QXP_UART0_RX 1 582*4882a593Smuzhiyun #define IMX8QXP_UART0_RX_ADMA_FLEXCAN0_RX IMX8QXP_UART0_RX 2 583*4882a593Smuzhiyun #define IMX8QXP_UART0_RX_LSIO_GPIO1_IO21 IMX8QXP_UART0_RX 4 584*4882a593Smuzhiyun #define IMX8QXP_UART0_TX_ADMA_UART0_TX IMX8QXP_UART0_TX 0 585*4882a593Smuzhiyun #define IMX8QXP_UART0_TX_ADMA_MQS_L IMX8QXP_UART0_TX 1 586*4882a593Smuzhiyun #define IMX8QXP_UART0_TX_ADMA_FLEXCAN0_TX IMX8QXP_UART0_TX 2 587*4882a593Smuzhiyun #define IMX8QXP_UART0_TX_LSIO_GPIO1_IO22 IMX8QXP_UART0_TX 4 588*4882a593Smuzhiyun #define IMX8QXP_UART2_TX_ADMA_UART2_TX IMX8QXP_UART2_TX 0 589*4882a593Smuzhiyun #define IMX8QXP_UART2_TX_ADMA_FTM_CH1 IMX8QXP_UART2_TX 1 590*4882a593Smuzhiyun #define IMX8QXP_UART2_TX_ADMA_FLEXCAN1_TX IMX8QXP_UART2_TX 2 591*4882a593Smuzhiyun #define IMX8QXP_UART2_TX_LSIO_GPIO1_IO23 IMX8QXP_UART2_TX 4 592*4882a593Smuzhiyun #define IMX8QXP_UART2_RX_ADMA_UART2_RX IMX8QXP_UART2_RX 0 593*4882a593Smuzhiyun #define IMX8QXP_UART2_RX_ADMA_FTM_CH0 IMX8QXP_UART2_RX 1 594*4882a593Smuzhiyun #define IMX8QXP_UART2_RX_ADMA_FLEXCAN1_RX IMX8QXP_UART2_RX 2 595*4882a593Smuzhiyun #define IMX8QXP_UART2_RX_LSIO_GPIO1_IO24 IMX8QXP_UART2_RX 4 596*4882a593Smuzhiyun #define IMX8QXP_MIPI_DSI0_I2C0_SCL_MIPI_DSI0_I2C0_SCL IMX8QXP_MIPI_DSI0_I2C0_SCL 0 597*4882a593Smuzhiyun #define IMX8QXP_MIPI_DSI0_I2C0_SCL_MIPI_DSI1_GPIO0_IO02 IMX8QXP_MIPI_DSI0_I2C0_SCL 1 598*4882a593Smuzhiyun #define IMX8QXP_MIPI_DSI0_I2C0_SCL_LSIO_GPIO1_IO25 IMX8QXP_MIPI_DSI0_I2C0_SCL 4 599*4882a593Smuzhiyun #define IMX8QXP_MIPI_DSI0_I2C0_SDA_MIPI_DSI0_I2C0_SDA IMX8QXP_MIPI_DSI0_I2C0_SDA 0 600*4882a593Smuzhiyun #define IMX8QXP_MIPI_DSI0_I2C0_SDA_MIPI_DSI1_GPIO0_IO03 IMX8QXP_MIPI_DSI0_I2C0_SDA 1 601*4882a593Smuzhiyun #define IMX8QXP_MIPI_DSI0_I2C0_SDA_LSIO_GPIO1_IO26 IMX8QXP_MIPI_DSI0_I2C0_SDA 4 602*4882a593Smuzhiyun #define IMX8QXP_MIPI_DSI0_GPIO0_00_MIPI_DSI0_GPIO0_IO00 IMX8QXP_MIPI_DSI0_GPIO0_00 0 603*4882a593Smuzhiyun #define IMX8QXP_MIPI_DSI0_GPIO0_00_ADMA_I2C1_SCL IMX8QXP_MIPI_DSI0_GPIO0_00 1 604*4882a593Smuzhiyun #define IMX8QXP_MIPI_DSI0_GPIO0_00_MIPI_DSI0_PWM0_OUT IMX8QXP_MIPI_DSI0_GPIO0_00 2 605*4882a593Smuzhiyun #define IMX8QXP_MIPI_DSI0_GPIO0_00_LSIO_GPIO1_IO27 IMX8QXP_MIPI_DSI0_GPIO0_00 4 606*4882a593Smuzhiyun #define IMX8QXP_MIPI_DSI0_GPIO0_01_MIPI_DSI0_GPIO0_IO01 IMX8QXP_MIPI_DSI0_GPIO0_01 0 607*4882a593Smuzhiyun #define IMX8QXP_MIPI_DSI0_GPIO0_01_ADMA_I2C1_SDA IMX8QXP_MIPI_DSI0_GPIO0_01 1 608*4882a593Smuzhiyun #define IMX8QXP_MIPI_DSI0_GPIO0_01_LSIO_GPIO1_IO28 IMX8QXP_MIPI_DSI0_GPIO0_01 4 609*4882a593Smuzhiyun #define IMX8QXP_MIPI_DSI1_I2C0_SCL_MIPI_DSI1_I2C0_SCL IMX8QXP_MIPI_DSI1_I2C0_SCL 0 610*4882a593Smuzhiyun #define IMX8QXP_MIPI_DSI1_I2C0_SCL_MIPI_DSI0_GPIO0_IO02 IMX8QXP_MIPI_DSI1_I2C0_SCL 1 611*4882a593Smuzhiyun #define IMX8QXP_MIPI_DSI1_I2C0_SCL_LSIO_GPIO1_IO29 IMX8QXP_MIPI_DSI1_I2C0_SCL 4 612*4882a593Smuzhiyun #define IMX8QXP_MIPI_DSI1_I2C0_SDA_MIPI_DSI1_I2C0_SDA IMX8QXP_MIPI_DSI1_I2C0_SDA 0 613*4882a593Smuzhiyun #define IMX8QXP_MIPI_DSI1_I2C0_SDA_MIPI_DSI0_GPIO0_IO03 IMX8QXP_MIPI_DSI1_I2C0_SDA 1 614*4882a593Smuzhiyun #define IMX8QXP_MIPI_DSI1_I2C0_SDA_LSIO_GPIO1_IO30 IMX8QXP_MIPI_DSI1_I2C0_SDA 4 615*4882a593Smuzhiyun #define IMX8QXP_MIPI_DSI1_GPIO0_00_MIPI_DSI1_GPIO0_IO00 IMX8QXP_MIPI_DSI1_GPIO0_00 0 616*4882a593Smuzhiyun #define IMX8QXP_MIPI_DSI1_GPIO0_00_ADMA_I2C2_SCL IMX8QXP_MIPI_DSI1_GPIO0_00 1 617*4882a593Smuzhiyun #define IMX8QXP_MIPI_DSI1_GPIO0_00_MIPI_DSI1_PWM0_OUT IMX8QXP_MIPI_DSI1_GPIO0_00 2 618*4882a593Smuzhiyun #define IMX8QXP_MIPI_DSI1_GPIO0_00_LSIO_GPIO1_IO31 IMX8QXP_MIPI_DSI1_GPIO0_00 4 619*4882a593Smuzhiyun #define IMX8QXP_MIPI_DSI1_GPIO0_01_MIPI_DSI1_GPIO0_IO01 IMX8QXP_MIPI_DSI1_GPIO0_01 0 620*4882a593Smuzhiyun #define IMX8QXP_MIPI_DSI1_GPIO0_01_ADMA_I2C2_SDA IMX8QXP_MIPI_DSI1_GPIO0_01 1 621*4882a593Smuzhiyun #define IMX8QXP_MIPI_DSI1_GPIO0_01_LSIO_GPIO2_IO00 IMX8QXP_MIPI_DSI1_GPIO0_01 4 622*4882a593Smuzhiyun #define IMX8QXP_JTAG_TRST_B_SCU_JTAG_TRST_B IMX8QXP_JTAG_TRST_B 0 623*4882a593Smuzhiyun #define IMX8QXP_JTAG_TRST_B_SCU_WDOG0_WDOG_OUT IMX8QXP_JTAG_TRST_B 1 624*4882a593Smuzhiyun #define IMX8QXP_PMIC_I2C_SCL_SCU_PMIC_I2C_SCL IMX8QXP_PMIC_I2C_SCL 0 625*4882a593Smuzhiyun #define IMX8QXP_PMIC_I2C_SCL_SCU_GPIO0_IOXX_PMIC_A35_ON IMX8QXP_PMIC_I2C_SCL 1 626*4882a593Smuzhiyun #define IMX8QXP_PMIC_I2C_SCL_LSIO_GPIO2_IO01 IMX8QXP_PMIC_I2C_SCL 4 627*4882a593Smuzhiyun #define IMX8QXP_PMIC_I2C_SDA_SCU_PMIC_I2C_SDA IMX8QXP_PMIC_I2C_SDA 0 628*4882a593Smuzhiyun #define IMX8QXP_PMIC_I2C_SDA_SCU_GPIO0_IOXX_PMIC_GPU_ON IMX8QXP_PMIC_I2C_SDA 1 629*4882a593Smuzhiyun #define IMX8QXP_PMIC_I2C_SDA_LSIO_GPIO2_IO02 IMX8QXP_PMIC_I2C_SDA 4 630*4882a593Smuzhiyun #define IMX8QXP_PMIC_INT_B_SCU_DIMX8QXPMIC_INT_B IMX8QXP_PMIC_INT_B 0 631*4882a593Smuzhiyun #define IMX8QXP_SCU_GPIO0_00_SCU_GPIO0_IO00 IMX8QXP_SCU_GPIO0_00 0 632*4882a593Smuzhiyun #define IMX8QXP_SCU_GPIO0_00_SCU_UART0_RX IMX8QXP_SCU_GPIO0_00 1 633*4882a593Smuzhiyun #define IMX8QXP_SCU_GPIO0_00_M40_UART0_RX IMX8QXP_SCU_GPIO0_00 2 634*4882a593Smuzhiyun #define IMX8QXP_SCU_GPIO0_00_ADMA_UART3_RX IMX8QXP_SCU_GPIO0_00 3 635*4882a593Smuzhiyun #define IMX8QXP_SCU_GPIO0_00_LSIO_GPIO2_IO03 IMX8QXP_SCU_GPIO0_00 4 636*4882a593Smuzhiyun #define IMX8QXP_SCU_GPIO0_01_SCU_GPIO0_IO01 IMX8QXP_SCU_GPIO0_01 0 637*4882a593Smuzhiyun #define IMX8QXP_SCU_GPIO0_01_SCU_UART0_TX IMX8QXP_SCU_GPIO0_01 1 638*4882a593Smuzhiyun #define IMX8QXP_SCU_GPIO0_01_M40_UART0_TX IMX8QXP_SCU_GPIO0_01 2 639*4882a593Smuzhiyun #define IMX8QXP_SCU_GPIO0_01_ADMA_UART3_TX IMX8QXP_SCU_GPIO0_01 3 640*4882a593Smuzhiyun #define IMX8QXP_SCU_GPIO0_01_SCU_WDOG0_WDOG_OUT IMX8QXP_SCU_GPIO0_01 4 641*4882a593Smuzhiyun #define IMX8QXP_SCU_PMIC_STANDBY_SCU_DIMX8QXPMIC_STANDBY IMX8QXP_SCU_PMIC_STANDBY 0 642*4882a593Smuzhiyun #define IMX8QXP_SCU_BOOT_MODE0_SCU_DSC_BOOT_MODE0 IMX8QXP_SCU_BOOT_MODE0 0 643*4882a593Smuzhiyun #define IMX8QXP_SCU_BOOT_MODE1_SCU_DSC_BOOT_MODE1 IMX8QXP_SCU_BOOT_MODE1 0 644*4882a593Smuzhiyun #define IMX8QXP_SCU_BOOT_MODE2_SCU_DSC_BOOT_MODE2 IMX8QXP_SCU_BOOT_MODE2 0 645*4882a593Smuzhiyun #define IMX8QXP_SCU_BOOT_MODE2_SCU_PMIC_I2C_SDA IMX8QXP_SCU_BOOT_MODE2 1 646*4882a593Smuzhiyun #define IMX8QXP_SCU_BOOT_MODE3_SCU_DSC_BOOT_MODE3 IMX8QXP_SCU_BOOT_MODE3 0 647*4882a593Smuzhiyun #define IMX8QXP_SCU_BOOT_MODE3_SCU_PMIC_I2C_SCL IMX8QXP_SCU_BOOT_MODE3 1 648*4882a593Smuzhiyun #define IMX8QXP_SCU_BOOT_MODE3_SCU_DSC_RTC_CLOCK_OUTPUT_32K IMX8QXP_SCU_BOOT_MODE3 3 649*4882a593Smuzhiyun #define IMX8QXP_CSI_D00_CI_PI_D02 IMX8QXP_CSI_D00 0 650*4882a593Smuzhiyun #define IMX8QXP_CSI_D00_ADMA_SAI0_RXC IMX8QXP_CSI_D00 2 651*4882a593Smuzhiyun #define IMX8QXP_CSI_D01_CI_PI_D03 IMX8QXP_CSI_D01 0 652*4882a593Smuzhiyun #define IMX8QXP_CSI_D01_ADMA_SAI0_RXD IMX8QXP_CSI_D01 2 653*4882a593Smuzhiyun #define IMX8QXP_CSI_D02_CI_PI_D04 IMX8QXP_CSI_D02 0 654*4882a593Smuzhiyun #define IMX8QXP_CSI_D02_ADMA_SAI0_RXFS IMX8QXP_CSI_D02 2 655*4882a593Smuzhiyun #define IMX8QXP_CSI_D03_CI_PI_D05 IMX8QXP_CSI_D03 0 656*4882a593Smuzhiyun #define IMX8QXP_CSI_D03_ADMA_SAI2_RXC IMX8QXP_CSI_D03 2 657*4882a593Smuzhiyun #define IMX8QXP_CSI_D04_CI_PI_D06 IMX8QXP_CSI_D04 0 658*4882a593Smuzhiyun #define IMX8QXP_CSI_D04_ADMA_SAI2_RXD IMX8QXP_CSI_D04 2 659*4882a593Smuzhiyun #define IMX8QXP_CSI_D05_CI_PI_D07 IMX8QXP_CSI_D05 0 660*4882a593Smuzhiyun #define IMX8QXP_CSI_D05_ADMA_SAI2_RXFS IMX8QXP_CSI_D05 2 661*4882a593Smuzhiyun #define IMX8QXP_CSI_D06_CI_PI_D08 IMX8QXP_CSI_D06 0 662*4882a593Smuzhiyun #define IMX8QXP_CSI_D06_ADMA_SAI3_RXC IMX8QXP_CSI_D06 2 663*4882a593Smuzhiyun #define IMX8QXP_CSI_D07_CI_PI_D09 IMX8QXP_CSI_D07 0 664*4882a593Smuzhiyun #define IMX8QXP_CSI_D07_ADMA_SAI3_RXD IMX8QXP_CSI_D07 2 665*4882a593Smuzhiyun #define IMX8QXP_CSI_HSYNC_CI_PI_HSYNC IMX8QXP_CSI_HSYNC 0 666*4882a593Smuzhiyun #define IMX8QXP_CSI_HSYNC_CI_PI_D00 IMX8QXP_CSI_HSYNC 1 667*4882a593Smuzhiyun #define IMX8QXP_CSI_HSYNC_ADMA_SAI3_RXFS IMX8QXP_CSI_HSYNC 2 668*4882a593Smuzhiyun #define IMX8QXP_CSI_VSYNC_CI_PI_VSYNC IMX8QXP_CSI_VSYNC 0 669*4882a593Smuzhiyun #define IMX8QXP_CSI_VSYNC_CI_PI_D01 IMX8QXP_CSI_VSYNC 1 670*4882a593Smuzhiyun #define IMX8QXP_CSI_PCLK_CI_PI_PCLK IMX8QXP_CSI_PCLK 0 671*4882a593Smuzhiyun #define IMX8QXP_CSI_PCLK_MIPI_CSI0_I2C0_SCL IMX8QXP_CSI_PCLK 1 672*4882a593Smuzhiyun #define IMX8QXP_CSI_PCLK_ADMA_SPI1_SCK IMX8QXP_CSI_PCLK 3 673*4882a593Smuzhiyun #define IMX8QXP_CSI_PCLK_LSIO_GPIO3_IO00 IMX8QXP_CSI_PCLK 4 674*4882a593Smuzhiyun #define IMX8QXP_CSI_MCLK_CI_PI_MCLK IMX8QXP_CSI_MCLK 0 675*4882a593Smuzhiyun #define IMX8QXP_CSI_MCLK_MIPI_CSI0_I2C0_SDA IMX8QXP_CSI_MCLK 1 676*4882a593Smuzhiyun #define IMX8QXP_CSI_MCLK_ADMA_SPI1_SDO IMX8QXP_CSI_MCLK 3 677*4882a593Smuzhiyun #define IMX8QXP_CSI_MCLK_LSIO_GPIO3_IO01 IMX8QXP_CSI_MCLK 4 678*4882a593Smuzhiyun #define IMX8QXP_CSI_EN_CI_PI_EN IMX8QXP_CSI_EN 0 679*4882a593Smuzhiyun #define IMX8QXP_CSI_EN_CI_PI_I2C_SCL IMX8QXP_CSI_EN 1 680*4882a593Smuzhiyun #define IMX8QXP_CSI_EN_ADMA_I2C3_SCL IMX8QXP_CSI_EN 2 681*4882a593Smuzhiyun #define IMX8QXP_CSI_EN_ADMA_SPI1_SDI IMX8QXP_CSI_EN 3 682*4882a593Smuzhiyun #define IMX8QXP_CSI_EN_LSIO_GPIO3_IO02 IMX8QXP_CSI_EN 4 683*4882a593Smuzhiyun #define IMX8QXP_CSI_RESET_CI_PI_RESET IMX8QXP_CSI_RESET 0 684*4882a593Smuzhiyun #define IMX8QXP_CSI_RESET_CI_PI_I2C_SDA IMX8QXP_CSI_RESET 1 685*4882a593Smuzhiyun #define IMX8QXP_CSI_RESET_ADMA_I2C3_SDA IMX8QXP_CSI_RESET 2 686*4882a593Smuzhiyun #define IMX8QXP_CSI_RESET_ADMA_SPI1_CS0 IMX8QXP_CSI_RESET 3 687*4882a593Smuzhiyun #define IMX8QXP_CSI_RESET_LSIO_GPIO3_IO03 IMX8QXP_CSI_RESET 4 688*4882a593Smuzhiyun #define IMX8QXP_MIPI_CSI0_MCLK_OUT_MIPI_CSI0_ACM_MCLK_OUT IMX8QXP_MIPI_CSI0_MCLK_OUT 0 689*4882a593Smuzhiyun #define IMX8QXP_MIPI_CSI0_MCLK_OUT_LSIO_GPIO3_IO04 IMX8QXP_MIPI_CSI0_MCLK_OUT 4 690*4882a593Smuzhiyun #define IMX8QXP_MIPI_CSI0_I2C0_SCL_MIPI_CSI0_I2C0_SCL IMX8QXP_MIPI_CSI0_I2C0_SCL 0 691*4882a593Smuzhiyun #define IMX8QXP_MIPI_CSI0_I2C0_SCL_MIPI_CSI0_GPIO0_IO02 IMX8QXP_MIPI_CSI0_I2C0_SCL 1 692*4882a593Smuzhiyun #define IMX8QXP_MIPI_CSI0_I2C0_SCL_LSIO_GPIO3_IO05 IMX8QXP_MIPI_CSI0_I2C0_SCL 4 693*4882a593Smuzhiyun #define IMX8QXP_MIPI_CSI0_I2C0_SDA_MIPI_CSI0_I2C0_SDA IMX8QXP_MIPI_CSI0_I2C0_SDA 0 694*4882a593Smuzhiyun #define IMX8QXP_MIPI_CSI0_I2C0_SDA_MIPI_CSI0_GPIO0_IO03 IMX8QXP_MIPI_CSI0_I2C0_SDA 1 695*4882a593Smuzhiyun #define IMX8QXP_MIPI_CSI0_I2C0_SDA_LSIO_GPIO3_IO06 IMX8QXP_MIPI_CSI0_I2C0_SDA 4 696*4882a593Smuzhiyun #define IMX8QXP_MIPI_CSI0_GPIO0_01_MIPI_CSI0_GPIO0_IO01 IMX8QXP_MIPI_CSI0_GPIO0_01 0 697*4882a593Smuzhiyun #define IMX8QXP_MIPI_CSI0_GPIO0_01_ADMA_I2C0_SDA IMX8QXP_MIPI_CSI0_GPIO0_01 1 698*4882a593Smuzhiyun #define IMX8QXP_MIPI_CSI0_GPIO0_01_LSIO_GPIO3_IO07 IMX8QXP_MIPI_CSI0_GPIO0_01 4 699*4882a593Smuzhiyun #define IMX8QXP_MIPI_CSI0_GPIO0_00_MIPI_CSI0_GPIO0_IO00 IMX8QXP_MIPI_CSI0_GPIO0_00 0 700*4882a593Smuzhiyun #define IMX8QXP_MIPI_CSI0_GPIO0_00_ADMA_I2C0_SCL IMX8QXP_MIPI_CSI0_GPIO0_00 1 701*4882a593Smuzhiyun #define IMX8QXP_MIPI_CSI0_GPIO0_00_LSIO_GPIO3_IO08 IMX8QXP_MIPI_CSI0_GPIO0_00 4 702*4882a593Smuzhiyun #define IMX8QXP_QSPI0A_DATA0_LSIO_QSPI0A_DATA0 IMX8QXP_QSPI0A_DATA0 0 703*4882a593Smuzhiyun #define IMX8QXP_QSPI0A_DATA0_LSIO_GPIO3_IO09 IMX8QXP_QSPI0A_DATA0 4 704*4882a593Smuzhiyun #define IMX8QXP_QSPI0A_DATA1_LSIO_QSPI0A_DATA1 IMX8QXP_QSPI0A_DATA1 0 705*4882a593Smuzhiyun #define IMX8QXP_QSPI0A_DATA1_LSIO_GPIO3_IO10 IMX8QXP_QSPI0A_DATA1 4 706*4882a593Smuzhiyun #define IMX8QXP_QSPI0A_DATA2_LSIO_QSPI0A_DATA2 IMX8QXP_QSPI0A_DATA2 0 707*4882a593Smuzhiyun #define IMX8QXP_QSPI0A_DATA2_LSIO_GPIO3_IO11 IMX8QXP_QSPI0A_DATA2 4 708*4882a593Smuzhiyun #define IMX8QXP_QSPI0A_DATA3_LSIO_QSPI0A_DATA3 IMX8QXP_QSPI0A_DATA3 0 709*4882a593Smuzhiyun #define IMX8QXP_QSPI0A_DATA3_LSIO_GPIO3_IO12 IMX8QXP_QSPI0A_DATA3 4 710*4882a593Smuzhiyun #define IMX8QXP_QSPI0A_DQS_LSIO_QSPI0A_DQS IMX8QXP_QSPI0A_DQS 0 711*4882a593Smuzhiyun #define IMX8QXP_QSPI0A_DQS_LSIO_GPIO3_IO13 IMX8QXP_QSPI0A_DQS 4 712*4882a593Smuzhiyun #define IMX8QXP_QSPI0A_SS0_B_LSIO_QSPI0A_SS0_B IMX8QXP_QSPI0A_SS0_B 0 713*4882a593Smuzhiyun #define IMX8QXP_QSPI0A_SS0_B_LSIO_GPIO3_IO14 IMX8QXP_QSPI0A_SS0_B 4 714*4882a593Smuzhiyun #define IMX8QXP_QSPI0A_SS1_B_LSIO_QSPI0A_SS1_B IMX8QXP_QSPI0A_SS1_B 0 715*4882a593Smuzhiyun #define IMX8QXP_QSPI0A_SS1_B_LSIO_GPIO3_IO15 IMX8QXP_QSPI0A_SS1_B 4 716*4882a593Smuzhiyun #define IMX8QXP_QSPI0A_SCLK_LSIO_QSPI0A_SCLK IMX8QXP_QSPI0A_SCLK 0 717*4882a593Smuzhiyun #define IMX8QXP_QSPI0A_SCLK_LSIO_GPIO3_IO16 IMX8QXP_QSPI0A_SCLK 4 718*4882a593Smuzhiyun #define IMX8QXP_QSPI0B_SCLK_LSIO_QSPI0B_SCLK IMX8QXP_QSPI0B_SCLK 0 719*4882a593Smuzhiyun #define IMX8QXP_QSPI0B_SCLK_LSIO_QSPI1A_SCLK IMX8QXP_QSPI0B_SCLK 1 720*4882a593Smuzhiyun #define IMX8QXP_QSPI0B_SCLK_LSIO_KPP0_COL0 IMX8QXP_QSPI0B_SCLK 2 721*4882a593Smuzhiyun #define IMX8QXP_QSPI0B_SCLK_LSIO_GPIO3_IO17 IMX8QXP_QSPI0B_SCLK 4 722*4882a593Smuzhiyun #define IMX8QXP_QSPI0B_DATA0_LSIO_QSPI0B_DATA0 IMX8QXP_QSPI0B_DATA0 0 723*4882a593Smuzhiyun #define IMX8QXP_QSPI0B_DATA0_LSIO_QSPI1A_DATA0 IMX8QXP_QSPI0B_DATA0 1 724*4882a593Smuzhiyun #define IMX8QXP_QSPI0B_DATA0_LSIO_KPP0_COL1 IMX8QXP_QSPI0B_DATA0 2 725*4882a593Smuzhiyun #define IMX8QXP_QSPI0B_DATA0_LSIO_GPIO3_IO18 IMX8QXP_QSPI0B_DATA0 4 726*4882a593Smuzhiyun #define IMX8QXP_QSPI0B_DATA1_LSIO_QSPI0B_DATA1 IMX8QXP_QSPI0B_DATA1 0 727*4882a593Smuzhiyun #define IMX8QXP_QSPI0B_DATA1_LSIO_QSPI1A_DATA1 IMX8QXP_QSPI0B_DATA1 1 728*4882a593Smuzhiyun #define IMX8QXP_QSPI0B_DATA1_LSIO_KPP0_COL2 IMX8QXP_QSPI0B_DATA1 2 729*4882a593Smuzhiyun #define IMX8QXP_QSPI0B_DATA1_LSIO_GPIO3_IO19 IMX8QXP_QSPI0B_DATA1 4 730*4882a593Smuzhiyun #define IMX8QXP_QSPI0B_DATA2_LSIO_QSPI0B_DATA2 IMX8QXP_QSPI0B_DATA2 0 731*4882a593Smuzhiyun #define IMX8QXP_QSPI0B_DATA2_LSIO_QSPI1A_DATA2 IMX8QXP_QSPI0B_DATA2 1 732*4882a593Smuzhiyun #define IMX8QXP_QSPI0B_DATA2_LSIO_KPP0_COL3 IMX8QXP_QSPI0B_DATA2 2 733*4882a593Smuzhiyun #define IMX8QXP_QSPI0B_DATA2_LSIO_GPIO3_IO20 IMX8QXP_QSPI0B_DATA2 4 734*4882a593Smuzhiyun #define IMX8QXP_QSPI0B_DATA3_LSIO_QSPI0B_DATA3 IMX8QXP_QSPI0B_DATA3 0 735*4882a593Smuzhiyun #define IMX8QXP_QSPI0B_DATA3_LSIO_QSPI1A_DATA3 IMX8QXP_QSPI0B_DATA3 1 736*4882a593Smuzhiyun #define IMX8QXP_QSPI0B_DATA3_LSIO_KPP0_ROW0 IMX8QXP_QSPI0B_DATA3 2 737*4882a593Smuzhiyun #define IMX8QXP_QSPI0B_DATA3_LSIO_GPIO3_IO21 IMX8QXP_QSPI0B_DATA3 4 738*4882a593Smuzhiyun #define IMX8QXP_QSPI0B_DQS_LSIO_QSPI0B_DQS IMX8QXP_QSPI0B_DQS 0 739*4882a593Smuzhiyun #define IMX8QXP_QSPI0B_DQS_LSIO_QSPI1A_DQS IMX8QXP_QSPI0B_DQS 1 740*4882a593Smuzhiyun #define IMX8QXP_QSPI0B_DQS_LSIO_KPP0_ROW1 IMX8QXP_QSPI0B_DQS 2 741*4882a593Smuzhiyun #define IMX8QXP_QSPI0B_DQS_LSIO_GPIO3_IO22 IMX8QXP_QSPI0B_DQS 4 742*4882a593Smuzhiyun #define IMX8QXP_QSPI0B_SS0_B_LSIO_QSPI0B_SS0_B IMX8QXP_QSPI0B_SS0_B 0 743*4882a593Smuzhiyun #define IMX8QXP_QSPI0B_SS0_B_LSIO_QSPI1A_SS0_B IMX8QXP_QSPI0B_SS0_B 1 744*4882a593Smuzhiyun #define IMX8QXP_QSPI0B_SS0_B_LSIO_KPP0_ROW2 IMX8QXP_QSPI0B_SS0_B 2 745*4882a593Smuzhiyun #define IMX8QXP_QSPI0B_SS0_B_LSIO_GPIO3_IO23 IMX8QXP_QSPI0B_SS0_B 4 746*4882a593Smuzhiyun #define IMX8QXP_QSPI0B_SS1_B_LSIO_QSPI0B_SS1_B IMX8QXP_QSPI0B_SS1_B 0 747*4882a593Smuzhiyun #define IMX8QXP_QSPI0B_SS1_B_LSIO_QSPI1A_SS1_B IMX8QXP_QSPI0B_SS1_B 1 748*4882a593Smuzhiyun #define IMX8QXP_QSPI0B_SS1_B_LSIO_KPP0_ROW3 IMX8QXP_QSPI0B_SS1_B 2 749*4882a593Smuzhiyun #define IMX8QXP_QSPI0B_SS1_B_LSIO_GPIO3_IO24 IMX8QXP_QSPI0B_SS1_B 4 750*4882a593Smuzhiyun 751*4882a593Smuzhiyun #endif /* _IMX8QXP_PADS_H */ 752