1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0+ */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (C) 2016 Freescale Semiconductor, Inc. 4*4882a593Smuzhiyun * Copyright 2017~2018 NXP 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #ifndef _IMX8QM_PADS_H 8*4882a593Smuzhiyun #define _IMX8QM_PADS_H 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun /* pin id */ 11*4882a593Smuzhiyun #define IMX8QM_SIM0_CLK 0 12*4882a593Smuzhiyun #define IMX8QM_SIM0_RST 1 13*4882a593Smuzhiyun #define IMX8QM_SIM0_IO 2 14*4882a593Smuzhiyun #define IMX8QM_SIM0_PD 3 15*4882a593Smuzhiyun #define IMX8QM_SIM0_POWER_EN 4 16*4882a593Smuzhiyun #define IMX8QM_SIM0_GPIO0_00 5 17*4882a593Smuzhiyun #define IMX8QM_COMP_CTL_GPIO_1V8_3V3_SIM 6 18*4882a593Smuzhiyun #define IMX8QM_M40_I2C0_SCL 7 19*4882a593Smuzhiyun #define IMX8QM_M40_I2C0_SDA 8 20*4882a593Smuzhiyun #define IMX8QM_M40_GPIO0_00 9 21*4882a593Smuzhiyun #define IMX8QM_M40_GPIO0_01 10 22*4882a593Smuzhiyun #define IMX8QM_M41_I2C0_SCL 11 23*4882a593Smuzhiyun #define IMX8QM_M41_I2C0_SDA 12 24*4882a593Smuzhiyun #define IMX8QM_M41_GPIO0_00 13 25*4882a593Smuzhiyun #define IMX8QM_M41_GPIO0_01 14 26*4882a593Smuzhiyun #define IMX8QM_GPT0_CLK 15 27*4882a593Smuzhiyun #define IMX8QM_GPT0_CAPTURE 16 28*4882a593Smuzhiyun #define IMX8QM_GPT0_COMPARE 17 29*4882a593Smuzhiyun #define IMX8QM_GPT1_CLK 18 30*4882a593Smuzhiyun #define IMX8QM_GPT1_CAPTURE 19 31*4882a593Smuzhiyun #define IMX8QM_GPT1_COMPARE 20 32*4882a593Smuzhiyun #define IMX8QM_UART0_RX 21 33*4882a593Smuzhiyun #define IMX8QM_UART0_TX 22 34*4882a593Smuzhiyun #define IMX8QM_UART0_RTS_B 23 35*4882a593Smuzhiyun #define IMX8QM_UART0_CTS_B 24 36*4882a593Smuzhiyun #define IMX8QM_UART1_TX 25 37*4882a593Smuzhiyun #define IMX8QM_UART1_RX 26 38*4882a593Smuzhiyun #define IMX8QM_UART1_RTS_B 27 39*4882a593Smuzhiyun #define IMX8QM_UART1_CTS_B 28 40*4882a593Smuzhiyun #define IMX8QM_COMP_CTL_GPIO_1V8_3V3_GPIOLH 29 41*4882a593Smuzhiyun #define IMX8QM_SCU_PMIC_MEMC_ON 30 42*4882a593Smuzhiyun #define IMX8QM_SCU_WDOG_OUT 31 43*4882a593Smuzhiyun #define IMX8QM_PMIC_I2C_SDA 32 44*4882a593Smuzhiyun #define IMX8QM_PMIC_I2C_SCL 33 45*4882a593Smuzhiyun #define IMX8QM_PMIC_EARLY_WARNING 34 46*4882a593Smuzhiyun #define IMX8QM_PMIC_INT_B 35 47*4882a593Smuzhiyun #define IMX8QM_SCU_GPIO0_00 36 48*4882a593Smuzhiyun #define IMX8QM_SCU_GPIO0_01 37 49*4882a593Smuzhiyun #define IMX8QM_SCU_GPIO0_02 38 50*4882a593Smuzhiyun #define IMX8QM_SCU_GPIO0_03 39 51*4882a593Smuzhiyun #define IMX8QM_SCU_GPIO0_04 40 52*4882a593Smuzhiyun #define IMX8QM_SCU_GPIO0_05 41 53*4882a593Smuzhiyun #define IMX8QM_SCU_GPIO0_06 42 54*4882a593Smuzhiyun #define IMX8QM_SCU_GPIO0_07 43 55*4882a593Smuzhiyun #define IMX8QM_SCU_BOOT_MODE0 44 56*4882a593Smuzhiyun #define IMX8QM_SCU_BOOT_MODE1 45 57*4882a593Smuzhiyun #define IMX8QM_SCU_BOOT_MODE2 46 58*4882a593Smuzhiyun #define IMX8QM_SCU_BOOT_MODE3 47 59*4882a593Smuzhiyun #define IMX8QM_SCU_BOOT_MODE4 48 60*4882a593Smuzhiyun #define IMX8QM_SCU_BOOT_MODE5 49 61*4882a593Smuzhiyun #define IMX8QM_LVDS0_GPIO00 50 62*4882a593Smuzhiyun #define IMX8QM_LVDS0_GPIO01 51 63*4882a593Smuzhiyun #define IMX8QM_LVDS0_I2C0_SCL 52 64*4882a593Smuzhiyun #define IMX8QM_LVDS0_I2C0_SDA 53 65*4882a593Smuzhiyun #define IMX8QM_LVDS0_I2C1_SCL 54 66*4882a593Smuzhiyun #define IMX8QM_LVDS0_I2C1_SDA 55 67*4882a593Smuzhiyun #define IMX8QM_LVDS1_GPIO00 56 68*4882a593Smuzhiyun #define IMX8QM_LVDS1_GPIO01 57 69*4882a593Smuzhiyun #define IMX8QM_LVDS1_I2C0_SCL 58 70*4882a593Smuzhiyun #define IMX8QM_LVDS1_I2C0_SDA 59 71*4882a593Smuzhiyun #define IMX8QM_LVDS1_I2C1_SCL 60 72*4882a593Smuzhiyun #define IMX8QM_LVDS1_I2C1_SDA 61 73*4882a593Smuzhiyun #define IMX8QM_COMP_CTL_GPIO_1V8_3V3_LVDSGPIO 62 74*4882a593Smuzhiyun #define IMX8QM_MIPI_DSI0_I2C0_SCL 63 75*4882a593Smuzhiyun #define IMX8QM_MIPI_DSI0_I2C0_SDA 64 76*4882a593Smuzhiyun #define IMX8QM_MIPI_DSI0_GPIO0_00 65 77*4882a593Smuzhiyun #define IMX8QM_MIPI_DSI0_GPIO0_01 66 78*4882a593Smuzhiyun #define IMX8QM_MIPI_DSI1_I2C0_SCL 67 79*4882a593Smuzhiyun #define IMX8QM_MIPI_DSI1_I2C0_SDA 68 80*4882a593Smuzhiyun #define IMX8QM_MIPI_DSI1_GPIO0_00 69 81*4882a593Smuzhiyun #define IMX8QM_MIPI_DSI1_GPIO0_01 70 82*4882a593Smuzhiyun #define IMX8QM_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO 71 83*4882a593Smuzhiyun #define IMX8QM_MIPI_CSI0_MCLK_OUT 72 84*4882a593Smuzhiyun #define IMX8QM_MIPI_CSI0_I2C0_SCL 73 85*4882a593Smuzhiyun #define IMX8QM_MIPI_CSI0_I2C0_SDA 74 86*4882a593Smuzhiyun #define IMX8QM_MIPI_CSI0_GPIO0_00 75 87*4882a593Smuzhiyun #define IMX8QM_MIPI_CSI0_GPIO0_01 76 88*4882a593Smuzhiyun #define IMX8QM_MIPI_CSI1_MCLK_OUT 77 89*4882a593Smuzhiyun #define IMX8QM_MIPI_CSI1_GPIO0_00 78 90*4882a593Smuzhiyun #define IMX8QM_MIPI_CSI1_GPIO0_01 79 91*4882a593Smuzhiyun #define IMX8QM_MIPI_CSI1_I2C0_SCL 80 92*4882a593Smuzhiyun #define IMX8QM_MIPI_CSI1_I2C0_SDA 81 93*4882a593Smuzhiyun #define IMX8QM_HDMI_TX0_TS_SCL 82 94*4882a593Smuzhiyun #define IMX8QM_HDMI_TX0_TS_SDA 83 95*4882a593Smuzhiyun #define IMX8QM_COMP_CTL_GPIO_3V3_HDMIGPIO 84 96*4882a593Smuzhiyun #define IMX8QM_ESAI1_FSR 85 97*4882a593Smuzhiyun #define IMX8QM_ESAI1_FST 86 98*4882a593Smuzhiyun #define IMX8QM_ESAI1_SCKR 87 99*4882a593Smuzhiyun #define IMX8QM_ESAI1_SCKT 88 100*4882a593Smuzhiyun #define IMX8QM_ESAI1_TX0 89 101*4882a593Smuzhiyun #define IMX8QM_ESAI1_TX1 90 102*4882a593Smuzhiyun #define IMX8QM_ESAI1_TX2_RX3 91 103*4882a593Smuzhiyun #define IMX8QM_ESAI1_TX3_RX2 92 104*4882a593Smuzhiyun #define IMX8QM_ESAI1_TX4_RX1 93 105*4882a593Smuzhiyun #define IMX8QM_ESAI1_TX5_RX0 94 106*4882a593Smuzhiyun #define IMX8QM_SPDIF0_RX 95 107*4882a593Smuzhiyun #define IMX8QM_SPDIF0_TX 96 108*4882a593Smuzhiyun #define IMX8QM_SPDIF0_EXT_CLK 97 109*4882a593Smuzhiyun #define IMX8QM_SPI3_SCK 98 110*4882a593Smuzhiyun #define IMX8QM_SPI3_SDO 99 111*4882a593Smuzhiyun #define IMX8QM_SPI3_SDI 100 112*4882a593Smuzhiyun #define IMX8QM_SPI3_CS0 101 113*4882a593Smuzhiyun #define IMX8QM_SPI3_CS1 102 114*4882a593Smuzhiyun #define IMX8QM_COMP_CTL_GPIO_1V8_3V3_GPIORHB 103 115*4882a593Smuzhiyun #define IMX8QM_ESAI0_FSR 104 116*4882a593Smuzhiyun #define IMX8QM_ESAI0_FST 105 117*4882a593Smuzhiyun #define IMX8QM_ESAI0_SCKR 106 118*4882a593Smuzhiyun #define IMX8QM_ESAI0_SCKT 107 119*4882a593Smuzhiyun #define IMX8QM_ESAI0_TX0 108 120*4882a593Smuzhiyun #define IMX8QM_ESAI0_TX1 109 121*4882a593Smuzhiyun #define IMX8QM_ESAI0_TX2_RX3 110 122*4882a593Smuzhiyun #define IMX8QM_ESAI0_TX3_RX2 111 123*4882a593Smuzhiyun #define IMX8QM_ESAI0_TX4_RX1 112 124*4882a593Smuzhiyun #define IMX8QM_ESAI0_TX5_RX0 113 125*4882a593Smuzhiyun #define IMX8QM_MCLK_IN0 114 126*4882a593Smuzhiyun #define IMX8QM_MCLK_OUT0 115 127*4882a593Smuzhiyun #define IMX8QM_COMP_CTL_GPIO_1V8_3V3_GPIORHC 116 128*4882a593Smuzhiyun #define IMX8QM_SPI0_SCK 117 129*4882a593Smuzhiyun #define IMX8QM_SPI0_SDO 118 130*4882a593Smuzhiyun #define IMX8QM_SPI0_SDI 119 131*4882a593Smuzhiyun #define IMX8QM_SPI0_CS0 120 132*4882a593Smuzhiyun #define IMX8QM_SPI0_CS1 121 133*4882a593Smuzhiyun #define IMX8QM_SPI2_SCK 122 134*4882a593Smuzhiyun #define IMX8QM_SPI2_SDO 123 135*4882a593Smuzhiyun #define IMX8QM_SPI2_SDI 124 136*4882a593Smuzhiyun #define IMX8QM_SPI2_CS0 125 137*4882a593Smuzhiyun #define IMX8QM_SPI2_CS1 126 138*4882a593Smuzhiyun #define IMX8QM_SAI1_RXC 127 139*4882a593Smuzhiyun #define IMX8QM_SAI1_RXD 128 140*4882a593Smuzhiyun #define IMX8QM_SAI1_RXFS 129 141*4882a593Smuzhiyun #define IMX8QM_SAI1_TXC 130 142*4882a593Smuzhiyun #define IMX8QM_SAI1_TXD 131 143*4882a593Smuzhiyun #define IMX8QM_SAI1_TXFS 132 144*4882a593Smuzhiyun #define IMX8QM_COMP_CTL_GPIO_1V8_3V3_GPIORHT 133 145*4882a593Smuzhiyun #define IMX8QM_ADC_IN7 134 146*4882a593Smuzhiyun #define IMX8QM_ADC_IN6 135 147*4882a593Smuzhiyun #define IMX8QM_ADC_IN5 136 148*4882a593Smuzhiyun #define IMX8QM_ADC_IN4 137 149*4882a593Smuzhiyun #define IMX8QM_ADC_IN3 138 150*4882a593Smuzhiyun #define IMX8QM_ADC_IN2 139 151*4882a593Smuzhiyun #define IMX8QM_ADC_IN1 140 152*4882a593Smuzhiyun #define IMX8QM_ADC_IN0 141 153*4882a593Smuzhiyun #define IMX8QM_MLB_SIG 142 154*4882a593Smuzhiyun #define IMX8QM_MLB_CLK 143 155*4882a593Smuzhiyun #define IMX8QM_MLB_DATA 144 156*4882a593Smuzhiyun #define IMX8QM_COMP_CTL_GPIO_1V8_3V3_GPIOLHT 145 157*4882a593Smuzhiyun #define IMX8QM_FLEXCAN0_RX 146 158*4882a593Smuzhiyun #define IMX8QM_FLEXCAN0_TX 147 159*4882a593Smuzhiyun #define IMX8QM_FLEXCAN1_RX 148 160*4882a593Smuzhiyun #define IMX8QM_FLEXCAN1_TX 149 161*4882a593Smuzhiyun #define IMX8QM_FLEXCAN2_RX 150 162*4882a593Smuzhiyun #define IMX8QM_FLEXCAN2_TX 151 163*4882a593Smuzhiyun #define IMX8QM_COMP_CTL_GPIO_1V8_3V3_GPIOTHR 152 164*4882a593Smuzhiyun #define IMX8QM_USB_SS3_TC0 153 165*4882a593Smuzhiyun #define IMX8QM_USB_SS3_TC1 154 166*4882a593Smuzhiyun #define IMX8QM_USB_SS3_TC2 155 167*4882a593Smuzhiyun #define IMX8QM_USB_SS3_TC3 156 168*4882a593Smuzhiyun #define IMX8QM_COMP_CTL_GPIO_3V3_USB3IO 157 169*4882a593Smuzhiyun #define IMX8QM_USDHC1_RESET_B 158 170*4882a593Smuzhiyun #define IMX8QM_USDHC1_VSELECT 159 171*4882a593Smuzhiyun #define IMX8QM_USDHC2_RESET_B 160 172*4882a593Smuzhiyun #define IMX8QM_USDHC2_VSELECT 161 173*4882a593Smuzhiyun #define IMX8QM_USDHC2_WP 162 174*4882a593Smuzhiyun #define IMX8QM_USDHC2_CD_B 163 175*4882a593Smuzhiyun #define IMX8QM_COMP_CTL_GPIO_1V8_3V3_VSELSEP 164 176*4882a593Smuzhiyun #define IMX8QM_ENET0_MDIO 165 177*4882a593Smuzhiyun #define IMX8QM_ENET0_MDC 166 178*4882a593Smuzhiyun #define IMX8QM_ENET0_REFCLK_125M_25M 167 179*4882a593Smuzhiyun #define IMX8QM_ENET1_REFCLK_125M_25M 168 180*4882a593Smuzhiyun #define IMX8QM_ENET1_MDIO 169 181*4882a593Smuzhiyun #define IMX8QM_ENET1_MDC 170 182*4882a593Smuzhiyun #define IMX8QM_COMP_CTL_GPIO_1V8_3V3_GPIOCT 171 183*4882a593Smuzhiyun #define IMX8QM_QSPI1A_SS0_B 172 184*4882a593Smuzhiyun #define IMX8QM_QSPI1A_SS1_B 173 185*4882a593Smuzhiyun #define IMX8QM_QSPI1A_SCLK 174 186*4882a593Smuzhiyun #define IMX8QM_QSPI1A_DQS 175 187*4882a593Smuzhiyun #define IMX8QM_QSPI1A_DATA3 176 188*4882a593Smuzhiyun #define IMX8QM_QSPI1A_DATA2 177 189*4882a593Smuzhiyun #define IMX8QM_QSPI1A_DATA1 178 190*4882a593Smuzhiyun #define IMX8QM_QSPI1A_DATA0 179 191*4882a593Smuzhiyun #define IMX8QM_COMP_CTL_GPIO_1V8_3V3_QSPI1 180 192*4882a593Smuzhiyun #define IMX8QM_QSPI0A_DATA0 181 193*4882a593Smuzhiyun #define IMX8QM_QSPI0A_DATA1 182 194*4882a593Smuzhiyun #define IMX8QM_QSPI0A_DATA2 183 195*4882a593Smuzhiyun #define IMX8QM_QSPI0A_DATA3 184 196*4882a593Smuzhiyun #define IMX8QM_QSPI0A_DQS 185 197*4882a593Smuzhiyun #define IMX8QM_QSPI0A_SS0_B 186 198*4882a593Smuzhiyun #define IMX8QM_QSPI0A_SS1_B 187 199*4882a593Smuzhiyun #define IMX8QM_QSPI0A_SCLK 188 200*4882a593Smuzhiyun #define IMX8QM_QSPI0B_SCLK 189 201*4882a593Smuzhiyun #define IMX8QM_QSPI0B_DATA0 190 202*4882a593Smuzhiyun #define IMX8QM_QSPI0B_DATA1 191 203*4882a593Smuzhiyun #define IMX8QM_QSPI0B_DATA2 192 204*4882a593Smuzhiyun #define IMX8QM_QSPI0B_DATA3 193 205*4882a593Smuzhiyun #define IMX8QM_QSPI0B_DQS 194 206*4882a593Smuzhiyun #define IMX8QM_QSPI0B_SS0_B 195 207*4882a593Smuzhiyun #define IMX8QM_QSPI0B_SS1_B 196 208*4882a593Smuzhiyun #define IMX8QM_COMP_CTL_GPIO_1V8_3V3_QSPI0 197 209*4882a593Smuzhiyun #define IMX8QM_PCIE_CTRL0_CLKREQ_B 198 210*4882a593Smuzhiyun #define IMX8QM_PCIE_CTRL0_WAKE_B 199 211*4882a593Smuzhiyun #define IMX8QM_PCIE_CTRL0_PERST_B 200 212*4882a593Smuzhiyun #define IMX8QM_PCIE_CTRL1_CLKREQ_B 201 213*4882a593Smuzhiyun #define IMX8QM_PCIE_CTRL1_WAKE_B 202 214*4882a593Smuzhiyun #define IMX8QM_PCIE_CTRL1_PERST_B 203 215*4882a593Smuzhiyun #define IMX8QM_COMP_CTL_GPIO_1V8_3V3_PCIESEP 204 216*4882a593Smuzhiyun #define IMX8QM_USB_HSIC0_DATA 205 217*4882a593Smuzhiyun #define IMX8QM_USB_HSIC0_STROBE 206 218*4882a593Smuzhiyun #define IMX8QM_CALIBRATION_0_HSIC 207 219*4882a593Smuzhiyun #define IMX8QM_CALIBRATION_1_HSIC 208 220*4882a593Smuzhiyun #define IMX8QM_EMMC0_CLK 209 221*4882a593Smuzhiyun #define IMX8QM_EMMC0_CMD 210 222*4882a593Smuzhiyun #define IMX8QM_EMMC0_DATA0 211 223*4882a593Smuzhiyun #define IMX8QM_EMMC0_DATA1 212 224*4882a593Smuzhiyun #define IMX8QM_EMMC0_DATA2 213 225*4882a593Smuzhiyun #define IMX8QM_EMMC0_DATA3 214 226*4882a593Smuzhiyun #define IMX8QM_EMMC0_DATA4 215 227*4882a593Smuzhiyun #define IMX8QM_EMMC0_DATA5 216 228*4882a593Smuzhiyun #define IMX8QM_EMMC0_DATA6 217 229*4882a593Smuzhiyun #define IMX8QM_EMMC0_DATA7 218 230*4882a593Smuzhiyun #define IMX8QM_EMMC0_STROBE 219 231*4882a593Smuzhiyun #define IMX8QM_EMMC0_RESET_B 220 232*4882a593Smuzhiyun #define IMX8QM_COMP_CTL_GPIO_1V8_3V3_SD1FIX 221 233*4882a593Smuzhiyun #define IMX8QM_USDHC1_CLK 222 234*4882a593Smuzhiyun #define IMX8QM_USDHC1_CMD 223 235*4882a593Smuzhiyun #define IMX8QM_USDHC1_DATA0 224 236*4882a593Smuzhiyun #define IMX8QM_USDHC1_DATA1 225 237*4882a593Smuzhiyun #define IMX8QM_CTL_NAND_RE_P_N 226 238*4882a593Smuzhiyun #define IMX8QM_USDHC1_DATA2 227 239*4882a593Smuzhiyun #define IMX8QM_USDHC1_DATA3 228 240*4882a593Smuzhiyun #define IMX8QM_CTL_NAND_DQS_P_N 229 241*4882a593Smuzhiyun #define IMX8QM_USDHC1_DATA4 230 242*4882a593Smuzhiyun #define IMX8QM_USDHC1_DATA5 231 243*4882a593Smuzhiyun #define IMX8QM_USDHC1_DATA6 232 244*4882a593Smuzhiyun #define IMX8QM_USDHC1_DATA7 233 245*4882a593Smuzhiyun #define IMX8QM_USDHC1_STROBE 234 246*4882a593Smuzhiyun #define IMX8QM_COMP_CTL_GPIO_1V8_3V3_VSEL2 235 247*4882a593Smuzhiyun #define IMX8QM_USDHC2_CLK 236 248*4882a593Smuzhiyun #define IMX8QM_USDHC2_CMD 237 249*4882a593Smuzhiyun #define IMX8QM_USDHC2_DATA0 238 250*4882a593Smuzhiyun #define IMX8QM_USDHC2_DATA1 239 251*4882a593Smuzhiyun #define IMX8QM_USDHC2_DATA2 240 252*4882a593Smuzhiyun #define IMX8QM_USDHC2_DATA3 241 253*4882a593Smuzhiyun #define IMX8QM_COMP_CTL_GPIO_1V8_3V3_VSEL3 242 254*4882a593Smuzhiyun #define IMX8QM_ENET0_RGMII_TXC 243 255*4882a593Smuzhiyun #define IMX8QM_ENET0_RGMII_TX_CTL 244 256*4882a593Smuzhiyun #define IMX8QM_ENET0_RGMII_TXD0 245 257*4882a593Smuzhiyun #define IMX8QM_ENET0_RGMII_TXD1 246 258*4882a593Smuzhiyun #define IMX8QM_ENET0_RGMII_TXD2 247 259*4882a593Smuzhiyun #define IMX8QM_ENET0_RGMII_TXD3 248 260*4882a593Smuzhiyun #define IMX8QM_ENET0_RGMII_RXC 249 261*4882a593Smuzhiyun #define IMX8QM_ENET0_RGMII_RX_CTL 250 262*4882a593Smuzhiyun #define IMX8QM_ENET0_RGMII_RXD0 251 263*4882a593Smuzhiyun #define IMX8QM_ENET0_RGMII_RXD1 252 264*4882a593Smuzhiyun #define IMX8QM_ENET0_RGMII_RXD2 253 265*4882a593Smuzhiyun #define IMX8QM_ENET0_RGMII_RXD3 254 266*4882a593Smuzhiyun #define IMX8QM_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB 255 267*4882a593Smuzhiyun #define IMX8QM_ENET1_RGMII_TXC 256 268*4882a593Smuzhiyun #define IMX8QM_ENET1_RGMII_TX_CTL 257 269*4882a593Smuzhiyun #define IMX8QM_ENET1_RGMII_TXD0 258 270*4882a593Smuzhiyun #define IMX8QM_ENET1_RGMII_TXD1 259 271*4882a593Smuzhiyun #define IMX8QM_ENET1_RGMII_TXD2 260 272*4882a593Smuzhiyun #define IMX8QM_ENET1_RGMII_TXD3 261 273*4882a593Smuzhiyun #define IMX8QM_ENET1_RGMII_RXC 262 274*4882a593Smuzhiyun #define IMX8QM_ENET1_RGMII_RX_CTL 263 275*4882a593Smuzhiyun #define IMX8QM_ENET1_RGMII_RXD0 264 276*4882a593Smuzhiyun #define IMX8QM_ENET1_RGMII_RXD1 265 277*4882a593Smuzhiyun #define IMX8QM_ENET1_RGMII_RXD2 266 278*4882a593Smuzhiyun #define IMX8QM_ENET1_RGMII_RXD3 267 279*4882a593Smuzhiyun #define IMX8QM_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA 268 280*4882a593Smuzhiyun 281*4882a593Smuzhiyun /* 282*4882a593Smuzhiyun * format: <pin_id mux_mode> 283*4882a593Smuzhiyun */ 284*4882a593Smuzhiyun #define IMX8QM_SIM0_CLK_DMA_SIM0_CLK IMX8QM_SIM0_CLK 0 285*4882a593Smuzhiyun #define IMX8QM_SIM0_CLK_LSIO_GPIO0_IO00 IMX8QM_SIM0_CLK 3 286*4882a593Smuzhiyun #define IMX8QM_SIM0_RST_DMA_SIM0_RST IMX8QM_SIM0_RST 0 287*4882a593Smuzhiyun #define IMX8QM_SIM0_RST_LSIO_GPIO0_IO01 IMX8QM_SIM0_RST 3 288*4882a593Smuzhiyun #define IMX8QM_SIM0_IO_DMA_SIM0_IO IMX8QM_SIM0_IO 0 289*4882a593Smuzhiyun #define IMX8QM_SIM0_IO_LSIO_GPIO0_IO02 IMX8QM_SIM0_IO 3 290*4882a593Smuzhiyun #define IMX8QM_SIM0_PD_DMA_SIM0_PD IMX8QM_SIM0_PD 0 291*4882a593Smuzhiyun #define IMX8QM_SIM0_PD_DMA_I2C3_SCL IMX8QM_SIM0_PD 1 292*4882a593Smuzhiyun #define IMX8QM_SIM0_PD_LSIO_GPIO0_IO03 IMX8QM_SIM0_PD 3 293*4882a593Smuzhiyun #define IMX8QM_SIM0_POWER_EN_DMA_SIM0_POWER_EN IMX8QM_SIM0_POWER_EN 0 294*4882a593Smuzhiyun #define IMX8QM_SIM0_POWER_EN_DMA_I2C3_SDA IMX8QM_SIM0_POWER_EN 1 295*4882a593Smuzhiyun #define IMX8QM_SIM0_POWER_EN_LSIO_GPIO0_IO04 IMX8QM_SIM0_POWER_EN 3 296*4882a593Smuzhiyun #define IMX8QM_SIM0_GPIO0_00_DMA_SIM0_POWER_EN IMX8QM_SIM0_GPIO0_00 0 297*4882a593Smuzhiyun #define IMX8QM_SIM0_GPIO0_00_LSIO_GPIO0_IO05 IMX8QM_SIM0_GPIO0_00 3 298*4882a593Smuzhiyun #define IMX8QM_M40_I2C0_SCL_M40_I2C0_SCL IMX8QM_M40_I2C0_SCL 0 299*4882a593Smuzhiyun #define IMX8QM_M40_I2C0_SCL_M40_UART0_RX IMX8QM_M40_I2C0_SCL 1 300*4882a593Smuzhiyun #define IMX8QM_M40_I2C0_SCL_M40_GPIO0_IO02 IMX8QM_M40_I2C0_SCL 2 301*4882a593Smuzhiyun #define IMX8QM_M40_I2C0_SCL_LSIO_GPIO0_IO06 IMX8QM_M40_I2C0_SCL 3 302*4882a593Smuzhiyun #define IMX8QM_M40_I2C0_SDA_M40_I2C0_SDA IMX8QM_M40_I2C0_SDA 0 303*4882a593Smuzhiyun #define IMX8QM_M40_I2C0_SDA_M40_UART0_TX IMX8QM_M40_I2C0_SDA 1 304*4882a593Smuzhiyun #define IMX8QM_M40_I2C0_SDA_M40_GPIO0_IO03 IMX8QM_M40_I2C0_SDA 2 305*4882a593Smuzhiyun #define IMX8QM_M40_I2C0_SDA_LSIO_GPIO0_IO07 IMX8QM_M40_I2C0_SDA 3 306*4882a593Smuzhiyun #define IMX8QM_M40_GPIO0_00_M40_GPIO0_IO00 IMX8QM_M40_GPIO0_00 0 307*4882a593Smuzhiyun #define IMX8QM_M40_GPIO0_00_M40_TPM0_CH0 IMX8QM_M40_GPIO0_00 1 308*4882a593Smuzhiyun #define IMX8QM_M40_GPIO0_00_DMA_UART4_RX IMX8QM_M40_GPIO0_00 2 309*4882a593Smuzhiyun #define IMX8QM_M40_GPIO0_00_LSIO_GPIO0_IO08 IMX8QM_M40_GPIO0_00 3 310*4882a593Smuzhiyun #define IMX8QM_M40_GPIO0_01_M40_GPIO0_IO01 IMX8QM_M40_GPIO0_01 0 311*4882a593Smuzhiyun #define IMX8QM_M40_GPIO0_01_M40_TPM0_CH1 IMX8QM_M40_GPIO0_01 1 312*4882a593Smuzhiyun #define IMX8QM_M40_GPIO0_01_DMA_UART4_TX IMX8QM_M40_GPIO0_01 2 313*4882a593Smuzhiyun #define IMX8QM_M40_GPIO0_01_LSIO_GPIO0_IO09 IMX8QM_M40_GPIO0_01 3 314*4882a593Smuzhiyun #define IMX8QM_M41_I2C0_SCL_M41_I2C0_SCL IMX8QM_M41_I2C0_SCL 0 315*4882a593Smuzhiyun #define IMX8QM_M41_I2C0_SCL_M41_UART0_RX IMX8QM_M41_I2C0_SCL 1 316*4882a593Smuzhiyun #define IMX8QM_M41_I2C0_SCL_M41_GPIO0_IO02 IMX8QM_M41_I2C0_SCL 2 317*4882a593Smuzhiyun #define IMX8QM_M41_I2C0_SCL_LSIO_GPIO0_IO10 IMX8QM_M41_I2C0_SCL 3 318*4882a593Smuzhiyun #define IMX8QM_M41_I2C0_SDA_M41_I2C0_SDA IMX8QM_M41_I2C0_SDA 0 319*4882a593Smuzhiyun #define IMX8QM_M41_I2C0_SDA_M41_UART0_TX IMX8QM_M41_I2C0_SDA 1 320*4882a593Smuzhiyun #define IMX8QM_M41_I2C0_SDA_M41_GPIO0_IO03 IMX8QM_M41_I2C0_SDA 2 321*4882a593Smuzhiyun #define IMX8QM_M41_I2C0_SDA_LSIO_GPIO0_IO11 IMX8QM_M41_I2C0_SDA 3 322*4882a593Smuzhiyun #define IMX8QM_M41_GPIO0_00_M41_GPIO0_IO00 IMX8QM_M41_GPIO0_00 0 323*4882a593Smuzhiyun #define IMX8QM_M41_GPIO0_00_M41_TPM0_CH0 IMX8QM_M41_GPIO0_00 1 324*4882a593Smuzhiyun #define IMX8QM_M41_GPIO0_00_DMA_UART3_RX IMX8QM_M41_GPIO0_00 2 325*4882a593Smuzhiyun #define IMX8QM_M41_GPIO0_00_LSIO_GPIO0_IO12 IMX8QM_M41_GPIO0_00 3 326*4882a593Smuzhiyun #define IMX8QM_M41_GPIO0_01_M41_GPIO0_IO01 IMX8QM_M41_GPIO0_01 0 327*4882a593Smuzhiyun #define IMX8QM_M41_GPIO0_01_M41_TPM0_CH1 IMX8QM_M41_GPIO0_01 1 328*4882a593Smuzhiyun #define IMX8QM_M41_GPIO0_01_DMA_UART3_TX IMX8QM_M41_GPIO0_01 2 329*4882a593Smuzhiyun #define IMX8QM_M41_GPIO0_01_LSIO_GPIO0_IO13 IMX8QM_M41_GPIO0_01 3 330*4882a593Smuzhiyun #define IMX8QM_GPT0_CLK_LSIO_GPT0_CLK IMX8QM_GPT0_CLK 0 331*4882a593Smuzhiyun #define IMX8QM_GPT0_CLK_DMA_I2C1_SCL IMX8QM_GPT0_CLK 1 332*4882a593Smuzhiyun #define IMX8QM_GPT0_CLK_LSIO_KPP0_COL4 IMX8QM_GPT0_CLK 2 333*4882a593Smuzhiyun #define IMX8QM_GPT0_CLK_LSIO_GPIO0_IO14 IMX8QM_GPT0_CLK 3 334*4882a593Smuzhiyun #define IMX8QM_GPT0_CAPTURE_LSIO_GPT0_CAPTURE IMX8QM_GPT0_CAPTURE 0 335*4882a593Smuzhiyun #define IMX8QM_GPT0_CAPTURE_DMA_I2C1_SDA IMX8QM_GPT0_CAPTURE 1 336*4882a593Smuzhiyun #define IMX8QM_GPT0_CAPTURE_LSIO_KPP0_COL5 IMX8QM_GPT0_CAPTURE 2 337*4882a593Smuzhiyun #define IMX8QM_GPT0_CAPTURE_LSIO_GPIO0_IO15 IMX8QM_GPT0_CAPTURE 3 338*4882a593Smuzhiyun #define IMX8QM_GPT0_COMPARE_LSIO_GPT0_COMPARE IMX8QM_GPT0_COMPARE 0 339*4882a593Smuzhiyun #define IMX8QM_GPT0_COMPARE_LSIO_PWM3_OUT IMX8QM_GPT0_COMPARE 1 340*4882a593Smuzhiyun #define IMX8QM_GPT0_COMPARE_LSIO_KPP0_COL6 IMX8QM_GPT0_COMPARE 2 341*4882a593Smuzhiyun #define IMX8QM_GPT0_COMPARE_LSIO_GPIO0_IO16 IMX8QM_GPT0_COMPARE 3 342*4882a593Smuzhiyun #define IMX8QM_GPT1_CLK_LSIO_GPT1_CLK IMX8QM_GPT1_CLK 0 343*4882a593Smuzhiyun #define IMX8QM_GPT1_CLK_DMA_I2C2_SCL IMX8QM_GPT1_CLK 1 344*4882a593Smuzhiyun #define IMX8QM_GPT1_CLK_LSIO_KPP0_COL7 IMX8QM_GPT1_CLK 2 345*4882a593Smuzhiyun #define IMX8QM_GPT1_CLK_LSIO_GPIO0_IO17 IMX8QM_GPT1_CLK 3 346*4882a593Smuzhiyun #define IMX8QM_GPT1_CAPTURE_LSIO_GPT1_CAPTURE IMX8QM_GPT1_CAPTURE 0 347*4882a593Smuzhiyun #define IMX8QM_GPT1_CAPTURE_DMA_I2C2_SDA IMX8QM_GPT1_CAPTURE 1 348*4882a593Smuzhiyun #define IMX8QM_GPT1_CAPTURE_LSIO_KPP0_ROW4 IMX8QM_GPT1_CAPTURE 2 349*4882a593Smuzhiyun #define IMX8QM_GPT1_CAPTURE_LSIO_GPIO0_IO18 IMX8QM_GPT1_CAPTURE 3 350*4882a593Smuzhiyun #define IMX8QM_GPT1_COMPARE_LSIO_GPT1_COMPARE IMX8QM_GPT1_COMPARE 0 351*4882a593Smuzhiyun #define IMX8QM_GPT1_COMPARE_LSIO_PWM2_OUT IMX8QM_GPT1_COMPARE 1 352*4882a593Smuzhiyun #define IMX8QM_GPT1_COMPARE_LSIO_KPP0_ROW5 IMX8QM_GPT1_COMPARE 2 353*4882a593Smuzhiyun #define IMX8QM_GPT1_COMPARE_LSIO_GPIO0_IO19 IMX8QM_GPT1_COMPARE 3 354*4882a593Smuzhiyun #define IMX8QM_UART0_RX_DMA_UART0_RX IMX8QM_UART0_RX 0 355*4882a593Smuzhiyun #define IMX8QM_UART0_RX_SCU_UART0_RX IMX8QM_UART0_RX 1 356*4882a593Smuzhiyun #define IMX8QM_UART0_RX_LSIO_GPIO0_IO20 IMX8QM_UART0_RX 3 357*4882a593Smuzhiyun #define IMX8QM_UART0_TX_DMA_UART0_TX IMX8QM_UART0_TX 0 358*4882a593Smuzhiyun #define IMX8QM_UART0_TX_SCU_UART0_TX IMX8QM_UART0_TX 1 359*4882a593Smuzhiyun #define IMX8QM_UART0_TX_LSIO_GPIO0_IO21 IMX8QM_UART0_TX 3 360*4882a593Smuzhiyun #define IMX8QM_UART0_RTS_B_DMA_UART0_RTS_B IMX8QM_UART0_RTS_B 0 361*4882a593Smuzhiyun #define IMX8QM_UART0_RTS_B_LSIO_PWM0_OUT IMX8QM_UART0_RTS_B 1 362*4882a593Smuzhiyun #define IMX8QM_UART0_RTS_B_DMA_UART2_RX IMX8QM_UART0_RTS_B 2 363*4882a593Smuzhiyun #define IMX8QM_UART0_RTS_B_LSIO_GPIO0_IO22 IMX8QM_UART0_RTS_B 3 364*4882a593Smuzhiyun #define IMX8QM_UART0_CTS_B_DMA_UART0_CTS_B IMX8QM_UART0_CTS_B 0 365*4882a593Smuzhiyun #define IMX8QM_UART0_CTS_B_LSIO_PWM1_OUT IMX8QM_UART0_CTS_B 1 366*4882a593Smuzhiyun #define IMX8QM_UART0_CTS_B_DMA_UART2_TX IMX8QM_UART0_CTS_B 2 367*4882a593Smuzhiyun #define IMX8QM_UART0_CTS_B_LSIO_GPIO0_IO23 IMX8QM_UART0_CTS_B 3 368*4882a593Smuzhiyun #define IMX8QM_UART1_TX_DMA_UART1_TX IMX8QM_UART1_TX 0 369*4882a593Smuzhiyun #define IMX8QM_UART1_TX_DMA_SPI3_SCK IMX8QM_UART1_TX 1 370*4882a593Smuzhiyun #define IMX8QM_UART1_TX_LSIO_GPIO0_IO24 IMX8QM_UART1_TX 3 371*4882a593Smuzhiyun #define IMX8QM_UART1_RX_DMA_UART1_RX IMX8QM_UART1_RX 0 372*4882a593Smuzhiyun #define IMX8QM_UART1_RX_DMA_SPI3_SDO IMX8QM_UART1_RX 1 373*4882a593Smuzhiyun #define IMX8QM_UART1_RX_LSIO_GPIO0_IO25 IMX8QM_UART1_RX 3 374*4882a593Smuzhiyun #define IMX8QM_UART1_RTS_B_DMA_UART1_RTS_B IMX8QM_UART1_RTS_B 0 375*4882a593Smuzhiyun #define IMX8QM_UART1_RTS_B_DMA_SPI3_SDI IMX8QM_UART1_RTS_B 1 376*4882a593Smuzhiyun #define IMX8QM_UART1_RTS_B_DMA_UART1_CTS_B IMX8QM_UART1_RTS_B 2 377*4882a593Smuzhiyun #define IMX8QM_UART1_RTS_B_LSIO_GPIO0_IO26 IMX8QM_UART1_RTS_B 3 378*4882a593Smuzhiyun #define IMX8QM_UART1_CTS_B_DMA_UART1_CTS_B IMX8QM_UART1_CTS_B 0 379*4882a593Smuzhiyun #define IMX8QM_UART1_CTS_B_DMA_SPI3_CS0 IMX8QM_UART1_CTS_B 1 380*4882a593Smuzhiyun #define IMX8QM_UART1_CTS_B_DMA_UART1_RTS_B IMX8QM_UART1_CTS_B 2 381*4882a593Smuzhiyun #define IMX8QM_UART1_CTS_B_LSIO_GPIO0_IO27 IMX8QM_UART1_CTS_B 3 382*4882a593Smuzhiyun #define IMX8QM_SCU_PMIC_MEMC_ON_SCU_GPIO0_IOXX_PMIC_MEMC_ON IMX8QM_SCU_PMIC_MEMC_ON 0 383*4882a593Smuzhiyun #define IMX8QM_SCU_WDOG_OUT_SCU_WDOG0_WDOG_OUT IMX8QM_SCU_WDOG_OUT 0 384*4882a593Smuzhiyun #define IMX8QM_PMIC_I2C_SDA_SCU_PMIC_I2C_SDA IMX8QM_PMIC_I2C_SDA 0 385*4882a593Smuzhiyun #define IMX8QM_PMIC_I2C_SCL_SCU_PMIC_I2C_SCL IMX8QM_PMIC_I2C_SCL 0 386*4882a593Smuzhiyun #define IMX8QM_PMIC_EARLY_WARNING_SCU_PMIC_EARLY_WARNING IMX8QM_PMIC_EARLY_WARNING 0 387*4882a593Smuzhiyun #define IMX8QM_PMIC_INT_B_SCU_DIMX8QMMIC_INT_B IMX8QM_PMIC_INT_B 0 388*4882a593Smuzhiyun #define IMX8QM_SCU_GPIO0_00_SCU_GPIO0_IO00 IMX8QM_SCU_GPIO0_00 0 389*4882a593Smuzhiyun #define IMX8QM_SCU_GPIO0_00_SCU_UART0_RX IMX8QM_SCU_GPIO0_00 1 390*4882a593Smuzhiyun #define IMX8QM_SCU_GPIO0_00_LSIO_GPIO0_IO28 IMX8QM_SCU_GPIO0_00 3 391*4882a593Smuzhiyun #define IMX8QM_SCU_GPIO0_01_SCU_GPIO0_IO01 IMX8QM_SCU_GPIO0_01 0 392*4882a593Smuzhiyun #define IMX8QM_SCU_GPIO0_01_SCU_UART0_TX IMX8QM_SCU_GPIO0_01 1 393*4882a593Smuzhiyun #define IMX8QM_SCU_GPIO0_01_LSIO_GPIO0_IO29 IMX8QM_SCU_GPIO0_01 3 394*4882a593Smuzhiyun #define IMX8QM_SCU_GPIO0_02_SCU_GPIO0_IO02 IMX8QM_SCU_GPIO0_02 0 395*4882a593Smuzhiyun #define IMX8QM_SCU_GPIO0_02_SCU_GPIO0_IOXX_PMIC_GPU0_ON IMX8QM_SCU_GPIO0_02 1 396*4882a593Smuzhiyun #define IMX8QM_SCU_GPIO0_02_LSIO_GPIO0_IO30 IMX8QM_SCU_GPIO0_02 3 397*4882a593Smuzhiyun #define IMX8QM_SCU_GPIO0_03_SCU_GPIO0_IO03 IMX8QM_SCU_GPIO0_03 0 398*4882a593Smuzhiyun #define IMX8QM_SCU_GPIO0_03_SCU_GPIO0_IOXX_PMIC_GPU1_ON IMX8QM_SCU_GPIO0_03 1 399*4882a593Smuzhiyun #define IMX8QM_SCU_GPIO0_03_LSIO_GPIO0_IO31 IMX8QM_SCU_GPIO0_03 3 400*4882a593Smuzhiyun #define IMX8QM_SCU_GPIO0_04_SCU_GPIO0_IO04 IMX8QM_SCU_GPIO0_04 0 401*4882a593Smuzhiyun #define IMX8QM_SCU_GPIO0_04_SCU_GPIO0_IOXX_PMIC_A72_ON IMX8QM_SCU_GPIO0_04 1 402*4882a593Smuzhiyun #define IMX8QM_SCU_GPIO0_04_LSIO_GPIO1_IO00 IMX8QM_SCU_GPIO0_04 3 403*4882a593Smuzhiyun #define IMX8QM_SCU_GPIO0_05_SCU_GPIO0_IO05 IMX8QM_SCU_GPIO0_05 0 404*4882a593Smuzhiyun #define IMX8QM_SCU_GPIO0_05_SCU_GPIO0_IOXX_PMIC_A53_ON IMX8QM_SCU_GPIO0_05 1 405*4882a593Smuzhiyun #define IMX8QM_SCU_GPIO0_05_LSIO_GPIO1_IO01 IMX8QM_SCU_GPIO0_05 3 406*4882a593Smuzhiyun #define IMX8QM_SCU_GPIO0_06_SCU_GPIO0_IO06 IMX8QM_SCU_GPIO0_06 0 407*4882a593Smuzhiyun #define IMX8QM_SCU_GPIO0_06_SCU_TPM0_CH0 IMX8QM_SCU_GPIO0_06 1 408*4882a593Smuzhiyun #define IMX8QM_SCU_GPIO0_06_LSIO_GPIO1_IO02 IMX8QM_SCU_GPIO0_06 3 409*4882a593Smuzhiyun #define IMX8QM_SCU_GPIO0_07_SCU_GPIO0_IO07 IMX8QM_SCU_GPIO0_07 0 410*4882a593Smuzhiyun #define IMX8QM_SCU_GPIO0_07_SCU_TPM0_CH1 IMX8QM_SCU_GPIO0_07 1 411*4882a593Smuzhiyun #define IMX8QM_SCU_GPIO0_07_SCU_DSC_RTC_CLOCK_OUTPUT_32K IMX8QM_SCU_GPIO0_07 2 412*4882a593Smuzhiyun #define IMX8QM_SCU_GPIO0_07_LSIO_GPIO1_IO03 IMX8QM_SCU_GPIO0_07 3 413*4882a593Smuzhiyun #define IMX8QM_SCU_BOOT_MODE0_SCU_DSC_BOOT_MODE0 IMX8QM_SCU_BOOT_MODE0 0 414*4882a593Smuzhiyun #define IMX8QM_SCU_BOOT_MODE1_SCU_DSC_BOOT_MODE1 IMX8QM_SCU_BOOT_MODE1 0 415*4882a593Smuzhiyun #define IMX8QM_SCU_BOOT_MODE2_SCU_DSC_BOOT_MODE2 IMX8QM_SCU_BOOT_MODE2 0 416*4882a593Smuzhiyun #define IMX8QM_SCU_BOOT_MODE3_SCU_DSC_BOOT_MODE3 IMX8QM_SCU_BOOT_MODE3 0 417*4882a593Smuzhiyun #define IMX8QM_SCU_BOOT_MODE4_SCU_DSC_BOOT_MODE4 IMX8QM_SCU_BOOT_MODE4 0 418*4882a593Smuzhiyun #define IMX8QM_SCU_BOOT_MODE4_SCU_PMIC_I2C_SCL IMX8QM_SCU_BOOT_MODE4 1 419*4882a593Smuzhiyun #define IMX8QM_SCU_BOOT_MODE5_SCU_DSC_BOOT_MODE5 IMX8QM_SCU_BOOT_MODE5 0 420*4882a593Smuzhiyun #define IMX8QM_SCU_BOOT_MODE5_SCU_PMIC_I2C_SDA IMX8QM_SCU_BOOT_MODE5 1 421*4882a593Smuzhiyun #define IMX8QM_LVDS0_GPIO00_LVDS0_GPIO0_IO00 IMX8QM_LVDS0_GPIO00 0 422*4882a593Smuzhiyun #define IMX8QM_LVDS0_GPIO00_LVDS0_PWM0_OUT IMX8QM_LVDS0_GPIO00 1 423*4882a593Smuzhiyun #define IMX8QM_LVDS0_GPIO00_LSIO_GPIO1_IO04 IMX8QM_LVDS0_GPIO00 3 424*4882a593Smuzhiyun #define IMX8QM_LVDS0_GPIO01_LVDS0_GPIO0_IO01 IMX8QM_LVDS0_GPIO01 0 425*4882a593Smuzhiyun #define IMX8QM_LVDS0_GPIO01_LSIO_GPIO1_IO05 IMX8QM_LVDS0_GPIO01 3 426*4882a593Smuzhiyun #define IMX8QM_LVDS0_I2C0_SCL_LVDS0_I2C0_SCL IMX8QM_LVDS0_I2C0_SCL 0 427*4882a593Smuzhiyun #define IMX8QM_LVDS0_I2C0_SCL_LVDS0_GPIO0_IO02 IMX8QM_LVDS0_I2C0_SCL 1 428*4882a593Smuzhiyun #define IMX8QM_LVDS0_I2C0_SCL_LSIO_GPIO1_IO06 IMX8QM_LVDS0_I2C0_SCL 3 429*4882a593Smuzhiyun #define IMX8QM_LVDS0_I2C0_SDA_LVDS0_I2C0_SDA IMX8QM_LVDS0_I2C0_SDA 0 430*4882a593Smuzhiyun #define IMX8QM_LVDS0_I2C0_SDA_LVDS0_GPIO0_IO03 IMX8QM_LVDS0_I2C0_SDA 1 431*4882a593Smuzhiyun #define IMX8QM_LVDS0_I2C0_SDA_LSIO_GPIO1_IO07 IMX8QM_LVDS0_I2C0_SDA 3 432*4882a593Smuzhiyun #define IMX8QM_LVDS0_I2C1_SCL_LVDS0_I2C1_SCL IMX8QM_LVDS0_I2C1_SCL 0 433*4882a593Smuzhiyun #define IMX8QM_LVDS0_I2C1_SCL_DMA_UART2_TX IMX8QM_LVDS0_I2C1_SCL 1 434*4882a593Smuzhiyun #define IMX8QM_LVDS0_I2C1_SCL_LSIO_GPIO1_IO08 IMX8QM_LVDS0_I2C1_SCL 3 435*4882a593Smuzhiyun #define IMX8QM_LVDS0_I2C1_SDA_LVDS0_I2C1_SDA IMX8QM_LVDS0_I2C1_SDA 0 436*4882a593Smuzhiyun #define IMX8QM_LVDS0_I2C1_SDA_DMA_UART2_RX IMX8QM_LVDS0_I2C1_SDA 1 437*4882a593Smuzhiyun #define IMX8QM_LVDS0_I2C1_SDA_LSIO_GPIO1_IO09 IMX8QM_LVDS0_I2C1_SDA 3 438*4882a593Smuzhiyun #define IMX8QM_LVDS1_GPIO00_LVDS1_GPIO0_IO00 IMX8QM_LVDS1_GPIO00 0 439*4882a593Smuzhiyun #define IMX8QM_LVDS1_GPIO00_LVDS1_PWM0_OUT IMX8QM_LVDS1_GPIO00 1 440*4882a593Smuzhiyun #define IMX8QM_LVDS1_GPIO00_LSIO_GPIO1_IO10 IMX8QM_LVDS1_GPIO00 3 441*4882a593Smuzhiyun #define IMX8QM_LVDS1_GPIO01_LVDS1_GPIO0_IO01 IMX8QM_LVDS1_GPIO01 0 442*4882a593Smuzhiyun #define IMX8QM_LVDS1_GPIO01_LSIO_GPIO1_IO11 IMX8QM_LVDS1_GPIO01 3 443*4882a593Smuzhiyun #define IMX8QM_LVDS1_I2C0_SCL_LVDS1_I2C0_SCL IMX8QM_LVDS1_I2C0_SCL 0 444*4882a593Smuzhiyun #define IMX8QM_LVDS1_I2C0_SCL_LVDS1_GPIO0_IO02 IMX8QM_LVDS1_I2C0_SCL 1 445*4882a593Smuzhiyun #define IMX8QM_LVDS1_I2C0_SCL_LSIO_GPIO1_IO12 IMX8QM_LVDS1_I2C0_SCL 3 446*4882a593Smuzhiyun #define IMX8QM_LVDS1_I2C0_SDA_LVDS1_I2C0_SDA IMX8QM_LVDS1_I2C0_SDA 0 447*4882a593Smuzhiyun #define IMX8QM_LVDS1_I2C0_SDA_LVDS1_GPIO0_IO03 IMX8QM_LVDS1_I2C0_SDA 1 448*4882a593Smuzhiyun #define IMX8QM_LVDS1_I2C0_SDA_LSIO_GPIO1_IO13 IMX8QM_LVDS1_I2C0_SDA 3 449*4882a593Smuzhiyun #define IMX8QM_LVDS1_I2C1_SCL_LVDS1_I2C1_SCL IMX8QM_LVDS1_I2C1_SCL 0 450*4882a593Smuzhiyun #define IMX8QM_LVDS1_I2C1_SCL_DMA_UART3_TX IMX8QM_LVDS1_I2C1_SCL 1 451*4882a593Smuzhiyun #define IMX8QM_LVDS1_I2C1_SCL_LSIO_GPIO1_IO14 IMX8QM_LVDS1_I2C1_SCL 3 452*4882a593Smuzhiyun #define IMX8QM_LVDS1_I2C1_SDA_LVDS1_I2C1_SDA IMX8QM_LVDS1_I2C1_SDA 0 453*4882a593Smuzhiyun #define IMX8QM_LVDS1_I2C1_SDA_DMA_UART3_RX IMX8QM_LVDS1_I2C1_SDA 1 454*4882a593Smuzhiyun #define IMX8QM_LVDS1_I2C1_SDA_LSIO_GPIO1_IO15 IMX8QM_LVDS1_I2C1_SDA 3 455*4882a593Smuzhiyun #define IMX8QM_MIPI_DSI0_I2C0_SCL_MIPI_DSI0_I2C0_SCL IMX8QM_MIPI_DSI0_I2C0_SCL 0 456*4882a593Smuzhiyun #define IMX8QM_MIPI_DSI0_I2C0_SCL_LSIO_GPIO1_IO16 IMX8QM_MIPI_DSI0_I2C0_SCL 3 457*4882a593Smuzhiyun #define IMX8QM_MIPI_DSI0_I2C0_SDA_MIPI_DSI0_I2C0_SDA IMX8QM_MIPI_DSI0_I2C0_SDA 0 458*4882a593Smuzhiyun #define IMX8QM_MIPI_DSI0_I2C0_SDA_LSIO_GPIO1_IO17 IMX8QM_MIPI_DSI0_I2C0_SDA 3 459*4882a593Smuzhiyun #define IMX8QM_MIPI_DSI0_GPIO0_00_MIPI_DSI0_GPIO0_IO00 IMX8QM_MIPI_DSI0_GPIO0_00 0 460*4882a593Smuzhiyun #define IMX8QM_MIPI_DSI0_GPIO0_00_MIPI_DSI0_PWM0_OUT IMX8QM_MIPI_DSI0_GPIO0_00 1 461*4882a593Smuzhiyun #define IMX8QM_MIPI_DSI0_GPIO0_00_LSIO_GPIO1_IO18 IMX8QM_MIPI_DSI0_GPIO0_00 3 462*4882a593Smuzhiyun #define IMX8QM_MIPI_DSI0_GPIO0_01_MIPI_DSI0_GPIO0_IO01 IMX8QM_MIPI_DSI0_GPIO0_01 0 463*4882a593Smuzhiyun #define IMX8QM_MIPI_DSI0_GPIO0_01_LSIO_GPIO1_IO19 IMX8QM_MIPI_DSI0_GPIO0_01 3 464*4882a593Smuzhiyun #define IMX8QM_MIPI_DSI1_I2C0_SCL_MIPI_DSI1_I2C0_SCL IMX8QM_MIPI_DSI1_I2C0_SCL 0 465*4882a593Smuzhiyun #define IMX8QM_MIPI_DSI1_I2C0_SCL_LSIO_GPIO1_IO20 IMX8QM_MIPI_DSI1_I2C0_SCL 3 466*4882a593Smuzhiyun #define IMX8QM_MIPI_DSI1_I2C0_SDA_MIPI_DSI1_I2C0_SDA IMX8QM_MIPI_DSI1_I2C0_SDA 0 467*4882a593Smuzhiyun #define IMX8QM_MIPI_DSI1_I2C0_SDA_LSIO_GPIO1_IO21 IMX8QM_MIPI_DSI1_I2C0_SDA 3 468*4882a593Smuzhiyun #define IMX8QM_MIPI_DSI1_GPIO0_00_MIPI_DSI1_GPIO0_IO00 IMX8QM_MIPI_DSI1_GPIO0_00 0 469*4882a593Smuzhiyun #define IMX8QM_MIPI_DSI1_GPIO0_00_MIPI_DSI1_PWM0_OUT IMX8QM_MIPI_DSI1_GPIO0_00 1 470*4882a593Smuzhiyun #define IMX8QM_MIPI_DSI1_GPIO0_00_LSIO_GPIO1_IO22 IMX8QM_MIPI_DSI1_GPIO0_00 3 471*4882a593Smuzhiyun #define IMX8QM_MIPI_DSI1_GPIO0_01_MIPI_DSI1_GPIO0_IO01 IMX8QM_MIPI_DSI1_GPIO0_01 0 472*4882a593Smuzhiyun #define IMX8QM_MIPI_DSI1_GPIO0_01_LSIO_GPIO1_IO23 IMX8QM_MIPI_DSI1_GPIO0_01 3 473*4882a593Smuzhiyun #define IMX8QM_MIPI_CSI0_MCLK_OUT_MIPI_CSI0_ACM_MCLK_OUT IMX8QM_MIPI_CSI0_MCLK_OUT 0 474*4882a593Smuzhiyun #define IMX8QM_MIPI_CSI0_MCLK_OUT_LSIO_GPIO1_IO24 IMX8QM_MIPI_CSI0_MCLK_OUT 3 475*4882a593Smuzhiyun #define IMX8QM_MIPI_CSI0_I2C0_SCL_MIPI_CSI0_I2C0_SCL IMX8QM_MIPI_CSI0_I2C0_SCL 0 476*4882a593Smuzhiyun #define IMX8QM_MIPI_CSI0_I2C0_SCL_LSIO_GPIO1_IO25 IMX8QM_MIPI_CSI0_I2C0_SCL 3 477*4882a593Smuzhiyun #define IMX8QM_MIPI_CSI0_I2C0_SDA_MIPI_CSI0_I2C0_SDA IMX8QM_MIPI_CSI0_I2C0_SDA 0 478*4882a593Smuzhiyun #define IMX8QM_MIPI_CSI0_I2C0_SDA_LSIO_GPIO1_IO26 IMX8QM_MIPI_CSI0_I2C0_SDA 3 479*4882a593Smuzhiyun #define IMX8QM_MIPI_CSI0_GPIO0_00_MIPI_CSI0_GPIO0_IO00 IMX8QM_MIPI_CSI0_GPIO0_00 0 480*4882a593Smuzhiyun #define IMX8QM_MIPI_CSI0_GPIO0_00_DMA_I2C0_SCL IMX8QM_MIPI_CSI0_GPIO0_00 1 481*4882a593Smuzhiyun #define IMX8QM_MIPI_CSI0_GPIO0_00_MIPI_CSI1_I2C0_SCL IMX8QM_MIPI_CSI0_GPIO0_00 2 482*4882a593Smuzhiyun #define IMX8QM_MIPI_CSI0_GPIO0_00_LSIO_GPIO1_IO27 IMX8QM_MIPI_CSI0_GPIO0_00 3 483*4882a593Smuzhiyun #define IMX8QM_MIPI_CSI0_GPIO0_01_MIPI_CSI0_GPIO0_IO01 IMX8QM_MIPI_CSI0_GPIO0_01 0 484*4882a593Smuzhiyun #define IMX8QM_MIPI_CSI0_GPIO0_01_DMA_I2C0_SDA IMX8QM_MIPI_CSI0_GPIO0_01 1 485*4882a593Smuzhiyun #define IMX8QM_MIPI_CSI0_GPIO0_01_MIPI_CSI1_I2C0_SDA IMX8QM_MIPI_CSI0_GPIO0_01 2 486*4882a593Smuzhiyun #define IMX8QM_MIPI_CSI0_GPIO0_01_LSIO_GPIO1_IO28 IMX8QM_MIPI_CSI0_GPIO0_01 3 487*4882a593Smuzhiyun #define IMX8QM_MIPI_CSI1_MCLK_OUT_MIPI_CSI1_ACM_MCLK_OUT IMX8QM_MIPI_CSI1_MCLK_OUT 0 488*4882a593Smuzhiyun #define IMX8QM_MIPI_CSI1_MCLK_OUT_LSIO_GPIO1_IO29 IMX8QM_MIPI_CSI1_MCLK_OUT 3 489*4882a593Smuzhiyun #define IMX8QM_MIPI_CSI1_GPIO0_00_MIPI_CSI1_GPIO0_IO00 IMX8QM_MIPI_CSI1_GPIO0_00 0 490*4882a593Smuzhiyun #define IMX8QM_MIPI_CSI1_GPIO0_00_DMA_UART4_RX IMX8QM_MIPI_CSI1_GPIO0_00 1 491*4882a593Smuzhiyun #define IMX8QM_MIPI_CSI1_GPIO0_00_LSIO_GPIO1_IO30 IMX8QM_MIPI_CSI1_GPIO0_00 3 492*4882a593Smuzhiyun #define IMX8QM_MIPI_CSI1_GPIO0_01_MIPI_CSI1_GPIO0_IO01 IMX8QM_MIPI_CSI1_GPIO0_01 0 493*4882a593Smuzhiyun #define IMX8QM_MIPI_CSI1_GPIO0_01_DMA_UART4_TX IMX8QM_MIPI_CSI1_GPIO0_01 1 494*4882a593Smuzhiyun #define IMX8QM_MIPI_CSI1_GPIO0_01_LSIO_GPIO1_IO31 IMX8QM_MIPI_CSI1_GPIO0_01 3 495*4882a593Smuzhiyun #define IMX8QM_MIPI_CSI1_I2C0_SCL_MIPI_CSI1_I2C0_SCL IMX8QM_MIPI_CSI1_I2C0_SCL 0 496*4882a593Smuzhiyun #define IMX8QM_MIPI_CSI1_I2C0_SCL_LSIO_GPIO2_IO00 IMX8QM_MIPI_CSI1_I2C0_SCL 3 497*4882a593Smuzhiyun #define IMX8QM_MIPI_CSI1_I2C0_SDA_MIPI_CSI1_I2C0_SDA IMX8QM_MIPI_CSI1_I2C0_SDA 0 498*4882a593Smuzhiyun #define IMX8QM_MIPI_CSI1_I2C0_SDA_LSIO_GPIO2_IO01 IMX8QM_MIPI_CSI1_I2C0_SDA 3 499*4882a593Smuzhiyun #define IMX8QM_HDMI_TX0_TS_SCL_HDMI_TX0_I2C0_SCL IMX8QM_HDMI_TX0_TS_SCL 0 500*4882a593Smuzhiyun #define IMX8QM_HDMI_TX0_TS_SCL_DMA_I2C0_SCL IMX8QM_HDMI_TX0_TS_SCL 1 501*4882a593Smuzhiyun #define IMX8QM_HDMI_TX0_TS_SCL_LSIO_GPIO2_IO02 IMX8QM_HDMI_TX0_TS_SCL 3 502*4882a593Smuzhiyun #define IMX8QM_HDMI_TX0_TS_SDA_HDMI_TX0_I2C0_SDA IMX8QM_HDMI_TX0_TS_SDA 0 503*4882a593Smuzhiyun #define IMX8QM_HDMI_TX0_TS_SDA_DMA_I2C0_SDA IMX8QM_HDMI_TX0_TS_SDA 1 504*4882a593Smuzhiyun #define IMX8QM_HDMI_TX0_TS_SDA_LSIO_GPIO2_IO03 IMX8QM_HDMI_TX0_TS_SDA 3 505*4882a593Smuzhiyun #define IMX8QM_ESAI1_FSR_AUD_ESAI1_FSR IMX8QM_ESAI1_FSR 0 506*4882a593Smuzhiyun #define IMX8QM_ESAI1_FSR_LSIO_GPIO2_IO04 IMX8QM_ESAI1_FSR 3 507*4882a593Smuzhiyun #define IMX8QM_ESAI1_FST_AUD_ESAI1_FST IMX8QM_ESAI1_FST 0 508*4882a593Smuzhiyun #define IMX8QM_ESAI1_FST_AUD_SPDIF0_EXT_CLK IMX8QM_ESAI1_FST 1 509*4882a593Smuzhiyun #define IMX8QM_ESAI1_FST_LSIO_GPIO2_IO05 IMX8QM_ESAI1_FST 3 510*4882a593Smuzhiyun #define IMX8QM_ESAI1_SCKR_AUD_ESAI1_SCKR IMX8QM_ESAI1_SCKR 0 511*4882a593Smuzhiyun #define IMX8QM_ESAI1_SCKR_LSIO_GPIO2_IO06 IMX8QM_ESAI1_SCKR 3 512*4882a593Smuzhiyun #define IMX8QM_ESAI1_SCKT_AUD_ESAI1_SCKT IMX8QM_ESAI1_SCKT 0 513*4882a593Smuzhiyun #define IMX8QM_ESAI1_SCKT_AUD_SAI2_RXC IMX8QM_ESAI1_SCKT 1 514*4882a593Smuzhiyun #define IMX8QM_ESAI1_SCKT_AUD_SPDIF0_EXT_CLK IMX8QM_ESAI1_SCKT 2 515*4882a593Smuzhiyun #define IMX8QM_ESAI1_SCKT_LSIO_GPIO2_IO07 IMX8QM_ESAI1_SCKT 3 516*4882a593Smuzhiyun #define IMX8QM_ESAI1_TX0_AUD_ESAI1_TX0 IMX8QM_ESAI1_TX0 0 517*4882a593Smuzhiyun #define IMX8QM_ESAI1_TX0_AUD_SAI2_RXD IMX8QM_ESAI1_TX0 1 518*4882a593Smuzhiyun #define IMX8QM_ESAI1_TX0_AUD_SPDIF0_RX IMX8QM_ESAI1_TX0 2 519*4882a593Smuzhiyun #define IMX8QM_ESAI1_TX0_LSIO_GPIO2_IO08 IMX8QM_ESAI1_TX0 3 520*4882a593Smuzhiyun #define IMX8QM_ESAI1_TX1_AUD_ESAI1_TX1 IMX8QM_ESAI1_TX1 0 521*4882a593Smuzhiyun #define IMX8QM_ESAI1_TX1_AUD_SAI2_RXFS IMX8QM_ESAI1_TX1 1 522*4882a593Smuzhiyun #define IMX8QM_ESAI1_TX1_AUD_SPDIF0_TX IMX8QM_ESAI1_TX1 2 523*4882a593Smuzhiyun #define IMX8QM_ESAI1_TX1_LSIO_GPIO2_IO09 IMX8QM_ESAI1_TX1 3 524*4882a593Smuzhiyun #define IMX8QM_ESAI1_TX2_RX3_AUD_ESAI1_TX2_RX3 IMX8QM_ESAI1_TX2_RX3 0 525*4882a593Smuzhiyun #define IMX8QM_ESAI1_TX2_RX3_AUD_SPDIF0_RX IMX8QM_ESAI1_TX2_RX3 1 526*4882a593Smuzhiyun #define IMX8QM_ESAI1_TX2_RX3_LSIO_GPIO2_IO10 IMX8QM_ESAI1_TX2_RX3 3 527*4882a593Smuzhiyun #define IMX8QM_ESAI1_TX3_RX2_AUD_ESAI1_TX3_RX2 IMX8QM_ESAI1_TX3_RX2 0 528*4882a593Smuzhiyun #define IMX8QM_ESAI1_TX3_RX2_AUD_SPDIF0_TX IMX8QM_ESAI1_TX3_RX2 1 529*4882a593Smuzhiyun #define IMX8QM_ESAI1_TX3_RX2_LSIO_GPIO2_IO11 IMX8QM_ESAI1_TX3_RX2 3 530*4882a593Smuzhiyun #define IMX8QM_ESAI1_TX4_RX1_AUD_ESAI1_TX4_RX1 IMX8QM_ESAI1_TX4_RX1 0 531*4882a593Smuzhiyun #define IMX8QM_ESAI1_TX4_RX1_LSIO_GPIO2_IO12 IMX8QM_ESAI1_TX4_RX1 3 532*4882a593Smuzhiyun #define IMX8QM_ESAI1_TX5_RX0_AUD_ESAI1_TX5_RX0 IMX8QM_ESAI1_TX5_RX0 0 533*4882a593Smuzhiyun #define IMX8QM_ESAI1_TX5_RX0_LSIO_GPIO2_IO13 IMX8QM_ESAI1_TX5_RX0 3 534*4882a593Smuzhiyun #define IMX8QM_SPDIF0_RX_AUD_SPDIF0_RX IMX8QM_SPDIF0_RX 0 535*4882a593Smuzhiyun #define IMX8QM_SPDIF0_RX_AUD_MQS_R IMX8QM_SPDIF0_RX 1 536*4882a593Smuzhiyun #define IMX8QM_SPDIF0_RX_AUD_ACM_MCLK_IN1 IMX8QM_SPDIF0_RX 2 537*4882a593Smuzhiyun #define IMX8QM_SPDIF0_RX_LSIO_GPIO2_IO14 IMX8QM_SPDIF0_RX 3 538*4882a593Smuzhiyun #define IMX8QM_SPDIF0_TX_AUD_SPDIF0_TX IMX8QM_SPDIF0_TX 0 539*4882a593Smuzhiyun #define IMX8QM_SPDIF0_TX_AUD_MQS_L IMX8QM_SPDIF0_TX 1 540*4882a593Smuzhiyun #define IMX8QM_SPDIF0_TX_AUD_ACM_MCLK_OUT1 IMX8QM_SPDIF0_TX 2 541*4882a593Smuzhiyun #define IMX8QM_SPDIF0_TX_LSIO_GPIO2_IO15 IMX8QM_SPDIF0_TX 3 542*4882a593Smuzhiyun #define IMX8QM_SPDIF0_EXT_CLK_AUD_SPDIF0_EXT_CLK IMX8QM_SPDIF0_EXT_CLK 0 543*4882a593Smuzhiyun #define IMX8QM_SPDIF0_EXT_CLK_DMA_DMA0_REQ_IN0 IMX8QM_SPDIF0_EXT_CLK 1 544*4882a593Smuzhiyun #define IMX8QM_SPDIF0_EXT_CLK_LSIO_GPIO2_IO16 IMX8QM_SPDIF0_EXT_CLK 3 545*4882a593Smuzhiyun #define IMX8QM_SPI3_SCK_DMA_SPI3_SCK IMX8QM_SPI3_SCK 0 546*4882a593Smuzhiyun #define IMX8QM_SPI3_SCK_LSIO_GPIO2_IO17 IMX8QM_SPI3_SCK 3 547*4882a593Smuzhiyun #define IMX8QM_SPI3_SDO_DMA_SPI3_SDO IMX8QM_SPI3_SDO 0 548*4882a593Smuzhiyun #define IMX8QM_SPI3_SDO_DMA_FTM_CH0 IMX8QM_SPI3_SDO 1 549*4882a593Smuzhiyun #define IMX8QM_SPI3_SDO_LSIO_GPIO2_IO18 IMX8QM_SPI3_SDO 3 550*4882a593Smuzhiyun #define IMX8QM_SPI3_SDI_DMA_SPI3_SDI IMX8QM_SPI3_SDI 0 551*4882a593Smuzhiyun #define IMX8QM_SPI3_SDI_DMA_FTM_CH1 IMX8QM_SPI3_SDI 1 552*4882a593Smuzhiyun #define IMX8QM_SPI3_SDI_LSIO_GPIO2_IO19 IMX8QM_SPI3_SDI 3 553*4882a593Smuzhiyun #define IMX8QM_SPI3_CS0_DMA_SPI3_CS0 IMX8QM_SPI3_CS0 0 554*4882a593Smuzhiyun #define IMX8QM_SPI3_CS0_DMA_FTM_CH2 IMX8QM_SPI3_CS0 1 555*4882a593Smuzhiyun #define IMX8QM_SPI3_CS0_LSIO_GPIO2_IO20 IMX8QM_SPI3_CS0 3 556*4882a593Smuzhiyun #define IMX8QM_SPI3_CS1_DMA_SPI3_CS1 IMX8QM_SPI3_CS1 0 557*4882a593Smuzhiyun #define IMX8QM_SPI3_CS1_LSIO_GPIO2_IO21 IMX8QM_SPI3_CS1 3 558*4882a593Smuzhiyun #define IMX8QM_ESAI0_FSR_AUD_ESAI0_FSR IMX8QM_ESAI0_FSR 0 559*4882a593Smuzhiyun #define IMX8QM_ESAI0_FSR_LSIO_GPIO2_IO22 IMX8QM_ESAI0_FSR 3 560*4882a593Smuzhiyun #define IMX8QM_ESAI0_FST_AUD_ESAI0_FST IMX8QM_ESAI0_FST 0 561*4882a593Smuzhiyun #define IMX8QM_ESAI0_FST_LSIO_GPIO2_IO23 IMX8QM_ESAI0_FST 3 562*4882a593Smuzhiyun #define IMX8QM_ESAI0_SCKR_AUD_ESAI0_SCKR IMX8QM_ESAI0_SCKR 0 563*4882a593Smuzhiyun #define IMX8QM_ESAI0_SCKR_LSIO_GPIO2_IO24 IMX8QM_ESAI0_SCKR 3 564*4882a593Smuzhiyun #define IMX8QM_ESAI0_SCKT_AUD_ESAI0_SCKT IMX8QM_ESAI0_SCKT 0 565*4882a593Smuzhiyun #define IMX8QM_ESAI0_SCKT_LSIO_GPIO2_IO25 IMX8QM_ESAI0_SCKT 3 566*4882a593Smuzhiyun #define IMX8QM_ESAI0_TX0_AUD_ESAI0_TX0 IMX8QM_ESAI0_TX0 0 567*4882a593Smuzhiyun #define IMX8QM_ESAI0_TX0_LSIO_GPIO2_IO26 IMX8QM_ESAI0_TX0 3 568*4882a593Smuzhiyun #define IMX8QM_ESAI0_TX1_AUD_ESAI0_TX1 IMX8QM_ESAI0_TX1 0 569*4882a593Smuzhiyun #define IMX8QM_ESAI0_TX1_LSIO_GPIO2_IO27 IMX8QM_ESAI0_TX1 3 570*4882a593Smuzhiyun #define IMX8QM_ESAI0_TX2_RX3_AUD_ESAI0_TX2_RX3 IMX8QM_ESAI0_TX2_RX3 0 571*4882a593Smuzhiyun #define IMX8QM_ESAI0_TX2_RX3_LSIO_GPIO2_IO28 IMX8QM_ESAI0_TX2_RX3 3 572*4882a593Smuzhiyun #define IMX8QM_ESAI0_TX3_RX2_AUD_ESAI0_TX3_RX2 IMX8QM_ESAI0_TX3_RX2 0 573*4882a593Smuzhiyun #define IMX8QM_ESAI0_TX3_RX2_LSIO_GPIO2_IO29 IMX8QM_ESAI0_TX3_RX2 3 574*4882a593Smuzhiyun #define IMX8QM_ESAI0_TX4_RX1_AUD_ESAI0_TX4_RX1 IMX8QM_ESAI0_TX4_RX1 0 575*4882a593Smuzhiyun #define IMX8QM_ESAI0_TX4_RX1_LSIO_GPIO2_IO30 IMX8QM_ESAI0_TX4_RX1 3 576*4882a593Smuzhiyun #define IMX8QM_ESAI0_TX5_RX0_AUD_ESAI0_TX5_RX0 IMX8QM_ESAI0_TX5_RX0 0 577*4882a593Smuzhiyun #define IMX8QM_ESAI0_TX5_RX0_LSIO_GPIO2_IO31 IMX8QM_ESAI0_TX5_RX0 3 578*4882a593Smuzhiyun #define IMX8QM_MCLK_IN0_AUD_ACM_MCLK_IN0 IMX8QM_MCLK_IN0 0 579*4882a593Smuzhiyun #define IMX8QM_MCLK_IN0_AUD_ESAI0_RX_HF_CLK IMX8QM_MCLK_IN0 1 580*4882a593Smuzhiyun #define IMX8QM_MCLK_IN0_AUD_ESAI1_RX_HF_CLK IMX8QM_MCLK_IN0 2 581*4882a593Smuzhiyun #define IMX8QM_MCLK_IN0_LSIO_GPIO3_IO00 IMX8QM_MCLK_IN0 3 582*4882a593Smuzhiyun #define IMX8QM_MCLK_OUT0_AUD_ACM_MCLK_OUT0 IMX8QM_MCLK_OUT0 0 583*4882a593Smuzhiyun #define IMX8QM_MCLK_OUT0_AUD_ESAI0_TX_HF_CLK IMX8QM_MCLK_OUT0 1 584*4882a593Smuzhiyun #define IMX8QM_MCLK_OUT0_AUD_ESAI1_TX_HF_CLK IMX8QM_MCLK_OUT0 2 585*4882a593Smuzhiyun #define IMX8QM_MCLK_OUT0_LSIO_GPIO3_IO01 IMX8QM_MCLK_OUT0 3 586*4882a593Smuzhiyun #define IMX8QM_SPI0_SCK_DMA_SPI0_SCK IMX8QM_SPI0_SCK 0 587*4882a593Smuzhiyun #define IMX8QM_SPI0_SCK_AUD_SAI0_RXC IMX8QM_SPI0_SCK 1 588*4882a593Smuzhiyun #define IMX8QM_SPI0_SCK_LSIO_GPIO3_IO02 IMX8QM_SPI0_SCK 3 589*4882a593Smuzhiyun #define IMX8QM_SPI0_SDO_DMA_SPI0_SDO IMX8QM_SPI0_SDO 0 590*4882a593Smuzhiyun #define IMX8QM_SPI0_SDO_AUD_SAI0_TXD IMX8QM_SPI0_SDO 1 591*4882a593Smuzhiyun #define IMX8QM_SPI0_SDO_LSIO_GPIO3_IO03 IMX8QM_SPI0_SDO 3 592*4882a593Smuzhiyun #define IMX8QM_SPI0_SDI_DMA_SPI0_SDI IMX8QM_SPI0_SDI 0 593*4882a593Smuzhiyun #define IMX8QM_SPI0_SDI_AUD_SAI0_RXD IMX8QM_SPI0_SDI 1 594*4882a593Smuzhiyun #define IMX8QM_SPI0_SDI_LSIO_GPIO3_IO04 IMX8QM_SPI0_SDI 3 595*4882a593Smuzhiyun #define IMX8QM_SPI0_CS0_DMA_SPI0_CS0 IMX8QM_SPI0_CS0 0 596*4882a593Smuzhiyun #define IMX8QM_SPI0_CS0_AUD_SAI0_RXFS IMX8QM_SPI0_CS0 1 597*4882a593Smuzhiyun #define IMX8QM_SPI0_CS0_LSIO_GPIO3_IO05 IMX8QM_SPI0_CS0 3 598*4882a593Smuzhiyun #define IMX8QM_SPI0_CS1_DMA_SPI0_CS1 IMX8QM_SPI0_CS1 0 599*4882a593Smuzhiyun #define IMX8QM_SPI0_CS1_AUD_SAI0_TXC IMX8QM_SPI0_CS1 1 600*4882a593Smuzhiyun #define IMX8QM_SPI0_CS1_LSIO_GPIO3_IO06 IMX8QM_SPI0_CS1 3 601*4882a593Smuzhiyun #define IMX8QM_SPI2_SCK_DMA_SPI2_SCK IMX8QM_SPI2_SCK 0 602*4882a593Smuzhiyun #define IMX8QM_SPI2_SCK_LSIO_GPIO3_IO07 IMX8QM_SPI2_SCK 3 603*4882a593Smuzhiyun #define IMX8QM_SPI2_SDO_DMA_SPI2_SDO IMX8QM_SPI2_SDO 0 604*4882a593Smuzhiyun #define IMX8QM_SPI2_SDO_LSIO_GPIO3_IO08 IMX8QM_SPI2_SDO 3 605*4882a593Smuzhiyun #define IMX8QM_SPI2_SDI_DMA_SPI2_SDI IMX8QM_SPI2_SDI 0 606*4882a593Smuzhiyun #define IMX8QM_SPI2_SDI_LSIO_GPIO3_IO09 IMX8QM_SPI2_SDI 3 607*4882a593Smuzhiyun #define IMX8QM_SPI2_CS0_DMA_SPI2_CS0 IMX8QM_SPI2_CS0 0 608*4882a593Smuzhiyun #define IMX8QM_SPI2_CS0_LSIO_GPIO3_IO10 IMX8QM_SPI2_CS0 3 609*4882a593Smuzhiyun #define IMX8QM_SPI2_CS1_DMA_SPI2_CS1 IMX8QM_SPI2_CS1 0 610*4882a593Smuzhiyun #define IMX8QM_SPI2_CS1_AUD_SAI0_TXFS IMX8QM_SPI2_CS1 1 611*4882a593Smuzhiyun #define IMX8QM_SPI2_CS1_LSIO_GPIO3_IO11 IMX8QM_SPI2_CS1 3 612*4882a593Smuzhiyun #define IMX8QM_SAI1_RXC_AUD_SAI1_RXC IMX8QM_SAI1_RXC 0 613*4882a593Smuzhiyun #define IMX8QM_SAI1_RXC_AUD_SAI0_TXD IMX8QM_SAI1_RXC 1 614*4882a593Smuzhiyun #define IMX8QM_SAI1_RXC_LSIO_GPIO3_IO12 IMX8QM_SAI1_RXC 3 615*4882a593Smuzhiyun #define IMX8QM_SAI1_RXD_AUD_SAI1_RXD IMX8QM_SAI1_RXD 0 616*4882a593Smuzhiyun #define IMX8QM_SAI1_RXD_AUD_SAI0_TXFS IMX8QM_SAI1_RXD 1 617*4882a593Smuzhiyun #define IMX8QM_SAI1_RXD_LSIO_GPIO3_IO13 IMX8QM_SAI1_RXD 3 618*4882a593Smuzhiyun #define IMX8QM_SAI1_RXFS_AUD_SAI1_RXFS IMX8QM_SAI1_RXFS 0 619*4882a593Smuzhiyun #define IMX8QM_SAI1_RXFS_AUD_SAI0_RXD IMX8QM_SAI1_RXFS 1 620*4882a593Smuzhiyun #define IMX8QM_SAI1_RXFS_LSIO_GPIO3_IO14 IMX8QM_SAI1_RXFS 3 621*4882a593Smuzhiyun #define IMX8QM_SAI1_TXC_AUD_SAI1_TXC IMX8QM_SAI1_TXC 0 622*4882a593Smuzhiyun #define IMX8QM_SAI1_TXC_AUD_SAI0_TXC IMX8QM_SAI1_TXC 1 623*4882a593Smuzhiyun #define IMX8QM_SAI1_TXC_LSIO_GPIO3_IO15 IMX8QM_SAI1_TXC 3 624*4882a593Smuzhiyun #define IMX8QM_SAI1_TXD_AUD_SAI1_TXD IMX8QM_SAI1_TXD 0 625*4882a593Smuzhiyun #define IMX8QM_SAI1_TXD_AUD_SAI1_RXC IMX8QM_SAI1_TXD 1 626*4882a593Smuzhiyun #define IMX8QM_SAI1_TXD_LSIO_GPIO3_IO16 IMX8QM_SAI1_TXD 3 627*4882a593Smuzhiyun #define IMX8QM_SAI1_TXFS_AUD_SAI1_TXFS IMX8QM_SAI1_TXFS 0 628*4882a593Smuzhiyun #define IMX8QM_SAI1_TXFS_AUD_SAI1_RXFS IMX8QM_SAI1_TXFS 1 629*4882a593Smuzhiyun #define IMX8QM_SAI1_TXFS_LSIO_GPIO3_IO17 IMX8QM_SAI1_TXFS 3 630*4882a593Smuzhiyun #define IMX8QM_ADC_IN7_DMA_ADC1_IN3 IMX8QM_ADC_IN7 0 631*4882a593Smuzhiyun #define IMX8QM_ADC_IN7_DMA_SPI1_CS1 IMX8QM_ADC_IN7 1 632*4882a593Smuzhiyun #define IMX8QM_ADC_IN7_LSIO_KPP0_ROW3 IMX8QM_ADC_IN7 2 633*4882a593Smuzhiyun #define IMX8QM_ADC_IN7_LSIO_GPIO3_IO25 IMX8QM_ADC_IN7 3 634*4882a593Smuzhiyun #define IMX8QM_ADC_IN6_DMA_ADC1_IN2 IMX8QM_ADC_IN6 0 635*4882a593Smuzhiyun #define IMX8QM_ADC_IN6_DMA_SPI1_CS0 IMX8QM_ADC_IN6 1 636*4882a593Smuzhiyun #define IMX8QM_ADC_IN6_LSIO_KPP0_ROW2 IMX8QM_ADC_IN6 2 637*4882a593Smuzhiyun #define IMX8QM_ADC_IN6_LSIO_GPIO3_IO24 IMX8QM_ADC_IN6 3 638*4882a593Smuzhiyun #define IMX8QM_ADC_IN5_DMA_ADC1_IN1 IMX8QM_ADC_IN5 0 639*4882a593Smuzhiyun #define IMX8QM_ADC_IN5_DMA_SPI1_SDI IMX8QM_ADC_IN5 1 640*4882a593Smuzhiyun #define IMX8QM_ADC_IN5_LSIO_KPP0_ROW1 IMX8QM_ADC_IN5 2 641*4882a593Smuzhiyun #define IMX8QM_ADC_IN5_LSIO_GPIO3_IO23 IMX8QM_ADC_IN5 3 642*4882a593Smuzhiyun #define IMX8QM_ADC_IN4_DMA_ADC1_IN0 IMX8QM_ADC_IN4 0 643*4882a593Smuzhiyun #define IMX8QM_ADC_IN4_DMA_SPI1_SDO IMX8QM_ADC_IN4 1 644*4882a593Smuzhiyun #define IMX8QM_ADC_IN4_LSIO_KPP0_ROW0 IMX8QM_ADC_IN4 2 645*4882a593Smuzhiyun #define IMX8QM_ADC_IN4_LSIO_GPIO3_IO22 IMX8QM_ADC_IN4 3 646*4882a593Smuzhiyun #define IMX8QM_ADC_IN3_DMA_ADC0_IN3 IMX8QM_ADC_IN3 0 647*4882a593Smuzhiyun #define IMX8QM_ADC_IN3_DMA_SPI1_SCK IMX8QM_ADC_IN3 1 648*4882a593Smuzhiyun #define IMX8QM_ADC_IN3_LSIO_KPP0_COL3 IMX8QM_ADC_IN3 2 649*4882a593Smuzhiyun #define IMX8QM_ADC_IN3_LSIO_GPIO3_IO21 IMX8QM_ADC_IN3 3 650*4882a593Smuzhiyun #define IMX8QM_ADC_IN2_DMA_ADC0_IN2 IMX8QM_ADC_IN2 0 651*4882a593Smuzhiyun #define IMX8QM_ADC_IN2_LSIO_KPP0_COL2 IMX8QM_ADC_IN2 2 652*4882a593Smuzhiyun #define IMX8QM_ADC_IN2_LSIO_GPIO3_IO20 IMX8QM_ADC_IN2 3 653*4882a593Smuzhiyun #define IMX8QM_ADC_IN1_DMA_ADC0_IN1 IMX8QM_ADC_IN1 0 654*4882a593Smuzhiyun #define IMX8QM_ADC_IN1_LSIO_KPP0_COL1 IMX8QM_ADC_IN1 2 655*4882a593Smuzhiyun #define IMX8QM_ADC_IN1_LSIO_GPIO3_IO19 IMX8QM_ADC_IN1 3 656*4882a593Smuzhiyun #define IMX8QM_ADC_IN0_DMA_ADC0_IN0 IMX8QM_ADC_IN0 0 657*4882a593Smuzhiyun #define IMX8QM_ADC_IN0_LSIO_KPP0_COL0 IMX8QM_ADC_IN0 2 658*4882a593Smuzhiyun #define IMX8QM_ADC_IN0_LSIO_GPIO3_IO18 IMX8QM_ADC_IN0 3 659*4882a593Smuzhiyun #define IMX8QM_MLB_SIG_CONN_MLB_SIG IMX8QM_MLB_SIG 0 660*4882a593Smuzhiyun #define IMX8QM_MLB_SIG_AUD_SAI3_RXC IMX8QM_MLB_SIG 1 661*4882a593Smuzhiyun #define IMX8QM_MLB_SIG_LSIO_GPIO3_IO26 IMX8QM_MLB_SIG 3 662*4882a593Smuzhiyun #define IMX8QM_MLB_CLK_CONN_MLB_CLK IMX8QM_MLB_CLK 0 663*4882a593Smuzhiyun #define IMX8QM_MLB_CLK_AUD_SAI3_RXFS IMX8QM_MLB_CLK 1 664*4882a593Smuzhiyun #define IMX8QM_MLB_CLK_LSIO_GPIO3_IO27 IMX8QM_MLB_CLK 3 665*4882a593Smuzhiyun #define IMX8QM_MLB_DATA_CONN_MLB_DATA IMX8QM_MLB_DATA 0 666*4882a593Smuzhiyun #define IMX8QM_MLB_DATA_AUD_SAI3_RXD IMX8QM_MLB_DATA 1 667*4882a593Smuzhiyun #define IMX8QM_MLB_DATA_LSIO_GPIO3_IO28 IMX8QM_MLB_DATA 3 668*4882a593Smuzhiyun #define IMX8QM_FLEXCAN0_RX_DMA_FLEXCAN0_RX IMX8QM_FLEXCAN0_RX 0 669*4882a593Smuzhiyun #define IMX8QM_FLEXCAN0_RX_LSIO_GPIO3_IO29 IMX8QM_FLEXCAN0_RX 3 670*4882a593Smuzhiyun #define IMX8QM_FLEXCAN0_TX_DMA_FLEXCAN0_TX IMX8QM_FLEXCAN0_TX 0 671*4882a593Smuzhiyun #define IMX8QM_FLEXCAN0_TX_LSIO_GPIO3_IO30 IMX8QM_FLEXCAN0_TX 3 672*4882a593Smuzhiyun #define IMX8QM_FLEXCAN1_RX_DMA_FLEXCAN1_RX IMX8QM_FLEXCAN1_RX 0 673*4882a593Smuzhiyun #define IMX8QM_FLEXCAN1_RX_LSIO_GPIO3_IO31 IMX8QM_FLEXCAN1_RX 3 674*4882a593Smuzhiyun #define IMX8QM_FLEXCAN1_TX_DMA_FLEXCAN1_TX IMX8QM_FLEXCAN1_TX 0 675*4882a593Smuzhiyun #define IMX8QM_FLEXCAN1_TX_LSIO_GPIO4_IO00 IMX8QM_FLEXCAN1_TX 3 676*4882a593Smuzhiyun #define IMX8QM_FLEXCAN2_RX_DMA_FLEXCAN2_RX IMX8QM_FLEXCAN2_RX 0 677*4882a593Smuzhiyun #define IMX8QM_FLEXCAN2_RX_LSIO_GPIO4_IO01 IMX8QM_FLEXCAN2_RX 3 678*4882a593Smuzhiyun #define IMX8QM_FLEXCAN2_TX_DMA_FLEXCAN2_TX IMX8QM_FLEXCAN2_TX 0 679*4882a593Smuzhiyun #define IMX8QM_FLEXCAN2_TX_LSIO_GPIO4_IO02 IMX8QM_FLEXCAN2_TX 3 680*4882a593Smuzhiyun #define IMX8QM_USB_SS3_TC0_DMA_I2C1_SCL IMX8QM_USB_SS3_TC0 0 681*4882a593Smuzhiyun #define IMX8QM_USB_SS3_TC0_CONN_USB_OTG1_PWR IMX8QM_USB_SS3_TC0 1 682*4882a593Smuzhiyun #define IMX8QM_USB_SS3_TC0_LSIO_GPIO4_IO03 IMX8QM_USB_SS3_TC0 3 683*4882a593Smuzhiyun #define IMX8QM_USB_SS3_TC1_DMA_I2C1_SCL IMX8QM_USB_SS3_TC1 0 684*4882a593Smuzhiyun #define IMX8QM_USB_SS3_TC1_CONN_USB_OTG2_PWR IMX8QM_USB_SS3_TC1 1 685*4882a593Smuzhiyun #define IMX8QM_USB_SS3_TC1_LSIO_GPIO4_IO04 IMX8QM_USB_SS3_TC1 3 686*4882a593Smuzhiyun #define IMX8QM_USB_SS3_TC2_DMA_I2C1_SDA IMX8QM_USB_SS3_TC2 0 687*4882a593Smuzhiyun #define IMX8QM_USB_SS3_TC2_CONN_USB_OTG1_OC IMX8QM_USB_SS3_TC2 1 688*4882a593Smuzhiyun #define IMX8QM_USB_SS3_TC2_LSIO_GPIO4_IO05 IMX8QM_USB_SS3_TC2 3 689*4882a593Smuzhiyun #define IMX8QM_USB_SS3_TC3_DMA_I2C1_SDA IMX8QM_USB_SS3_TC3 0 690*4882a593Smuzhiyun #define IMX8QM_USB_SS3_TC3_CONN_USB_OTG2_OC IMX8QM_USB_SS3_TC3 1 691*4882a593Smuzhiyun #define IMX8QM_USB_SS3_TC3_LSIO_GPIO4_IO06 IMX8QM_USB_SS3_TC3 3 692*4882a593Smuzhiyun #define IMX8QM_USDHC1_RESET_B_CONN_USDHC1_RESET_B IMX8QM_USDHC1_RESET_B 0 693*4882a593Smuzhiyun #define IMX8QM_USDHC1_RESET_B_LSIO_GPIO4_IO07 IMX8QM_USDHC1_RESET_B 3 694*4882a593Smuzhiyun #define IMX8QM_USDHC1_VSELECT_CONN_USDHC1_VSELECT IMX8QM_USDHC1_VSELECT 0 695*4882a593Smuzhiyun #define IMX8QM_USDHC1_VSELECT_LSIO_GPIO4_IO08 IMX8QM_USDHC1_VSELECT 3 696*4882a593Smuzhiyun #define IMX8QM_USDHC2_RESET_B_CONN_USDHC2_RESET_B IMX8QM_USDHC2_RESET_B 0 697*4882a593Smuzhiyun #define IMX8QM_USDHC2_RESET_B_LSIO_GPIO4_IO09 IMX8QM_USDHC2_RESET_B 3 698*4882a593Smuzhiyun #define IMX8QM_USDHC2_VSELECT_CONN_USDHC2_VSELECT IMX8QM_USDHC2_VSELECT 0 699*4882a593Smuzhiyun #define IMX8QM_USDHC2_VSELECT_LSIO_GPIO4_IO10 IMX8QM_USDHC2_VSELECT 3 700*4882a593Smuzhiyun #define IMX8QM_USDHC2_WP_CONN_USDHC2_WP IMX8QM_USDHC2_WP 0 701*4882a593Smuzhiyun #define IMX8QM_USDHC2_WP_LSIO_GPIO4_IO11 IMX8QM_USDHC2_WP 3 702*4882a593Smuzhiyun #define IMX8QM_USDHC2_CD_B_CONN_USDHC2_CD_B IMX8QM_USDHC2_CD_B 0 703*4882a593Smuzhiyun #define IMX8QM_USDHC2_CD_B_LSIO_GPIO4_IO12 IMX8QM_USDHC2_CD_B 3 704*4882a593Smuzhiyun #define IMX8QM_ENET0_MDIO_CONN_ENET0_MDIO IMX8QM_ENET0_MDIO 0 705*4882a593Smuzhiyun #define IMX8QM_ENET0_MDIO_DMA_I2C4_SDA IMX8QM_ENET0_MDIO 1 706*4882a593Smuzhiyun #define IMX8QM_ENET0_MDIO_LSIO_GPIO4_IO13 IMX8QM_ENET0_MDIO 3 707*4882a593Smuzhiyun #define IMX8QM_ENET0_MDC_CONN_ENET0_MDC IMX8QM_ENET0_MDC 0 708*4882a593Smuzhiyun #define IMX8QM_ENET0_MDC_DMA_I2C4_SCL IMX8QM_ENET0_MDC 1 709*4882a593Smuzhiyun #define IMX8QM_ENET0_MDC_LSIO_GPIO4_IO14 IMX8QM_ENET0_MDC 3 710*4882a593Smuzhiyun #define IMX8QM_ENET0_REFCLK_125M_25M_CONN_ENET0_REFCLK_125M_25M IMX8QM_ENET0_REFCLK_125M_25M 0 711*4882a593Smuzhiyun #define IMX8QM_ENET0_REFCLK_125M_25M_CONN_ENET0_PPS IMX8QM_ENET0_REFCLK_125M_25M 1 712*4882a593Smuzhiyun #define IMX8QM_ENET0_REFCLK_125M_25M_LSIO_GPIO4_IO15 IMX8QM_ENET0_REFCLK_125M_25M 3 713*4882a593Smuzhiyun #define IMX8QM_ENET1_REFCLK_125M_25M_CONN_ENET1_REFCLK_125M_25M IMX8QM_ENET1_REFCLK_125M_25M 0 714*4882a593Smuzhiyun #define IMX8QM_ENET1_REFCLK_125M_25M_CONN_ENET1_PPS IMX8QM_ENET1_REFCLK_125M_25M 1 715*4882a593Smuzhiyun #define IMX8QM_ENET1_REFCLK_125M_25M_LSIO_GPIO4_IO16 IMX8QM_ENET1_REFCLK_125M_25M 3 716*4882a593Smuzhiyun #define IMX8QM_ENET1_MDIO_CONN_ENET1_MDIO IMX8QM_ENET1_MDIO 0 717*4882a593Smuzhiyun #define IMX8QM_ENET1_MDIO_DMA_I2C4_SDA IMX8QM_ENET1_MDIO 1 718*4882a593Smuzhiyun #define IMX8QM_ENET1_MDIO_LSIO_GPIO4_IO17 IMX8QM_ENET1_MDIO 3 719*4882a593Smuzhiyun #define IMX8QM_ENET1_MDC_CONN_ENET1_MDC IMX8QM_ENET1_MDC 0 720*4882a593Smuzhiyun #define IMX8QM_ENET1_MDC_DMA_I2C4_SCL IMX8QM_ENET1_MDC 1 721*4882a593Smuzhiyun #define IMX8QM_ENET1_MDC_LSIO_GPIO4_IO18 IMX8QM_ENET1_MDC 3 722*4882a593Smuzhiyun #define IMX8QM_QSPI1A_SS0_B_LSIO_QSPI1A_SS0_B IMX8QM_QSPI1A_SS0_B 0 723*4882a593Smuzhiyun #define IMX8QM_QSPI1A_SS0_B_LSIO_GPIO4_IO19 IMX8QM_QSPI1A_SS0_B 3 724*4882a593Smuzhiyun #define IMX8QM_QSPI1A_SS1_B_LSIO_QSPI1A_SS1_B IMX8QM_QSPI1A_SS1_B 0 725*4882a593Smuzhiyun #define IMX8QM_QSPI1A_SS1_B_LSIO_QSPI1A_SCLK2 IMX8QM_QSPI1A_SS1_B 1 726*4882a593Smuzhiyun #define IMX8QM_QSPI1A_SS1_B_LSIO_GPIO4_IO20 IMX8QM_QSPI1A_SS1_B 3 727*4882a593Smuzhiyun #define IMX8QM_QSPI1A_SCLK_LSIO_QSPI1A_SCLK IMX8QM_QSPI1A_SCLK 0 728*4882a593Smuzhiyun #define IMX8QM_QSPI1A_SCLK_LSIO_GPIO4_IO21 IMX8QM_QSPI1A_SCLK 3 729*4882a593Smuzhiyun #define IMX8QM_QSPI1A_DQS_LSIO_QSPI1A_DQS IMX8QM_QSPI1A_DQS 0 730*4882a593Smuzhiyun #define IMX8QM_QSPI1A_DQS_LSIO_GPIO4_IO22 IMX8QM_QSPI1A_DQS 3 731*4882a593Smuzhiyun #define IMX8QM_QSPI1A_DATA3_LSIO_QSPI1A_DATA3 IMX8QM_QSPI1A_DATA3 0 732*4882a593Smuzhiyun #define IMX8QM_QSPI1A_DATA3_DMA_I2C1_SDA IMX8QM_QSPI1A_DATA3 1 733*4882a593Smuzhiyun #define IMX8QM_QSPI1A_DATA3_CONN_USB_OTG1_OC IMX8QM_QSPI1A_DATA3 2 734*4882a593Smuzhiyun #define IMX8QM_QSPI1A_DATA3_LSIO_GPIO4_IO23 IMX8QM_QSPI1A_DATA3 3 735*4882a593Smuzhiyun #define IMX8QM_QSPI1A_DATA2_LSIO_QSPI1A_DATA2 IMX8QM_QSPI1A_DATA2 0 736*4882a593Smuzhiyun #define IMX8QM_QSPI1A_DATA2_DMA_I2C1_SCL IMX8QM_QSPI1A_DATA2 1 737*4882a593Smuzhiyun #define IMX8QM_QSPI1A_DATA2_CONN_USB_OTG2_PWR IMX8QM_QSPI1A_DATA2 2 738*4882a593Smuzhiyun #define IMX8QM_QSPI1A_DATA2_LSIO_GPIO4_IO24 IMX8QM_QSPI1A_DATA2 3 739*4882a593Smuzhiyun #define IMX8QM_QSPI1A_DATA1_LSIO_QSPI1A_DATA1 IMX8QM_QSPI1A_DATA1 0 740*4882a593Smuzhiyun #define IMX8QM_QSPI1A_DATA1_DMA_I2C1_SDA IMX8QM_QSPI1A_DATA1 1 741*4882a593Smuzhiyun #define IMX8QM_QSPI1A_DATA1_CONN_USB_OTG2_OC IMX8QM_QSPI1A_DATA1 2 742*4882a593Smuzhiyun #define IMX8QM_QSPI1A_DATA1_LSIO_GPIO4_IO25 IMX8QM_QSPI1A_DATA1 3 743*4882a593Smuzhiyun #define IMX8QM_QSPI1A_DATA0_LSIO_QSPI1A_DATA0 IMX8QM_QSPI1A_DATA0 0 744*4882a593Smuzhiyun #define IMX8QM_QSPI1A_DATA0_LSIO_GPIO4_IO26 IMX8QM_QSPI1A_DATA0 3 745*4882a593Smuzhiyun #define IMX8QM_QSPI0A_DATA0_LSIO_QSPI0A_DATA0 IMX8QM_QSPI0A_DATA0 0 746*4882a593Smuzhiyun #define IMX8QM_QSPI0A_DATA1_LSIO_QSPI0A_DATA1 IMX8QM_QSPI0A_DATA1 0 747*4882a593Smuzhiyun #define IMX8QM_QSPI0A_DATA2_LSIO_QSPI0A_DATA2 IMX8QM_QSPI0A_DATA2 0 748*4882a593Smuzhiyun #define IMX8QM_QSPI0A_DATA3_LSIO_QSPI0A_DATA3 IMX8QM_QSPI0A_DATA3 0 749*4882a593Smuzhiyun #define IMX8QM_QSPI0A_DQS_LSIO_QSPI0A_DQS IMX8QM_QSPI0A_DQS 0 750*4882a593Smuzhiyun #define IMX8QM_QSPI0A_SS0_B_LSIO_QSPI0A_SS0_B IMX8QM_QSPI0A_SS0_B 0 751*4882a593Smuzhiyun #define IMX8QM_QSPI0A_SS1_B_LSIO_QSPI0A_SS1_B IMX8QM_QSPI0A_SS1_B 0 752*4882a593Smuzhiyun #define IMX8QM_QSPI0A_SS1_B_LSIO_QSPI0A_SCLK2 IMX8QM_QSPI0A_SS1_B 1 753*4882a593Smuzhiyun #define IMX8QM_QSPI0A_SCLK_LSIO_QSPI0A_SCLK IMX8QM_QSPI0A_SCLK 0 754*4882a593Smuzhiyun #define IMX8QM_QSPI0B_SCLK_LSIO_QSPI0B_SCLK IMX8QM_QSPI0B_SCLK 0 755*4882a593Smuzhiyun #define IMX8QM_QSPI0B_DATA0_LSIO_QSPI0B_DATA0 IMX8QM_QSPI0B_DATA0 0 756*4882a593Smuzhiyun #define IMX8QM_QSPI0B_DATA1_LSIO_QSPI0B_DATA1 IMX8QM_QSPI0B_DATA1 0 757*4882a593Smuzhiyun #define IMX8QM_QSPI0B_DATA2_LSIO_QSPI0B_DATA2 IMX8QM_QSPI0B_DATA2 0 758*4882a593Smuzhiyun #define IMX8QM_QSPI0B_DATA3_LSIO_QSPI0B_DATA3 IMX8QM_QSPI0B_DATA3 0 759*4882a593Smuzhiyun #define IMX8QM_QSPI0B_DQS_LSIO_QSPI0B_DQS IMX8QM_QSPI0B_DQS 0 760*4882a593Smuzhiyun #define IMX8QM_QSPI0B_SS0_B_LSIO_QSPI0B_SS0_B IMX8QM_QSPI0B_SS0_B 0 761*4882a593Smuzhiyun #define IMX8QM_QSPI0B_SS1_B_LSIO_QSPI0B_SS1_B IMX8QM_QSPI0B_SS1_B 0 762*4882a593Smuzhiyun #define IMX8QM_QSPI0B_SS1_B_LSIO_QSPI0B_SCLK2 IMX8QM_QSPI0B_SS1_B 1 763*4882a593Smuzhiyun #define IMX8QM_PCIE_CTRL0_CLKREQ_B_HSIO_PCIE0_CLKREQ_B IMX8QM_PCIE_CTRL0_CLKREQ_B 0 764*4882a593Smuzhiyun #define IMX8QM_PCIE_CTRL0_CLKREQ_B_LSIO_GPIO4_IO27 IMX8QM_PCIE_CTRL0_CLKREQ_B 3 765*4882a593Smuzhiyun #define IMX8QM_PCIE_CTRL0_WAKE_B_HSIO_PCIE0_WAKE_B IMX8QM_PCIE_CTRL0_WAKE_B 0 766*4882a593Smuzhiyun #define IMX8QM_PCIE_CTRL0_WAKE_B_LSIO_GPIO4_IO28 IMX8QM_PCIE_CTRL0_WAKE_B 3 767*4882a593Smuzhiyun #define IMX8QM_PCIE_CTRL0_PERST_B_HSIO_PCIE0_PERST_B IMX8QM_PCIE_CTRL0_PERST_B 0 768*4882a593Smuzhiyun #define IMX8QM_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO29 IMX8QM_PCIE_CTRL0_PERST_B 3 769*4882a593Smuzhiyun #define IMX8QM_PCIE_CTRL1_CLKREQ_B_HSIO_PCIE1_CLKREQ_B IMX8QM_PCIE_CTRL1_CLKREQ_B 0 770*4882a593Smuzhiyun #define IMX8QM_PCIE_CTRL1_CLKREQ_B_DMA_I2C1_SDA IMX8QM_PCIE_CTRL1_CLKREQ_B 1 771*4882a593Smuzhiyun #define IMX8QM_PCIE_CTRL1_CLKREQ_B_CONN_USB_OTG2_OC IMX8QM_PCIE_CTRL1_CLKREQ_B 2 772*4882a593Smuzhiyun #define IMX8QM_PCIE_CTRL1_CLKREQ_B_LSIO_GPIO4_IO30 IMX8QM_PCIE_CTRL1_CLKREQ_B 3 773*4882a593Smuzhiyun #define IMX8QM_PCIE_CTRL1_WAKE_B_HSIO_PCIE1_WAKE_B IMX8QM_PCIE_CTRL1_WAKE_B 0 774*4882a593Smuzhiyun #define IMX8QM_PCIE_CTRL1_WAKE_B_DMA_I2C1_SCL IMX8QM_PCIE_CTRL1_WAKE_B 1 775*4882a593Smuzhiyun #define IMX8QM_PCIE_CTRL1_WAKE_B_CONN_USB_OTG2_PWR IMX8QM_PCIE_CTRL1_WAKE_B 2 776*4882a593Smuzhiyun #define IMX8QM_PCIE_CTRL1_WAKE_B_LSIO_GPIO4_IO31 IMX8QM_PCIE_CTRL1_WAKE_B 3 777*4882a593Smuzhiyun #define IMX8QM_PCIE_CTRL1_PERST_B_HSIO_PCIE1_PERST_B IMX8QM_PCIE_CTRL1_PERST_B 0 778*4882a593Smuzhiyun #define IMX8QM_PCIE_CTRL1_PERST_B_DMA_I2C1_SCL IMX8QM_PCIE_CTRL1_PERST_B 1 779*4882a593Smuzhiyun #define IMX8QM_PCIE_CTRL1_PERST_B_CONN_USB_OTG1_PWR IMX8QM_PCIE_CTRL1_PERST_B 2 780*4882a593Smuzhiyun #define IMX8QM_PCIE_CTRL1_PERST_B_LSIO_GPIO5_IO00 IMX8QM_PCIE_CTRL1_PERST_B 3 781*4882a593Smuzhiyun #define IMX8QM_USB_HSIC0_DATA_CONN_USB_HSIC0_DATA IMX8QM_USB_HSIC0_DATA 0 782*4882a593Smuzhiyun #define IMX8QM_USB_HSIC0_DATA_DMA_I2C1_SDA IMX8QM_USB_HSIC0_DATA 1 783*4882a593Smuzhiyun #define IMX8QM_USB_HSIC0_DATA_LSIO_GPIO5_IO01 IMX8QM_USB_HSIC0_DATA 3 784*4882a593Smuzhiyun #define IMX8QM_USB_HSIC0_STROBE_CONN_USB_HSIC0_STROBE IMX8QM_USB_HSIC0_STROBE 0 785*4882a593Smuzhiyun #define IMX8QM_USB_HSIC0_STROBE_DMA_I2C1_SCL IMX8QM_USB_HSIC0_STROBE 1 786*4882a593Smuzhiyun #define IMX8QM_USB_HSIC0_STROBE_LSIO_GPIO5_IO02 IMX8QM_USB_HSIC0_STROBE 3 787*4882a593Smuzhiyun #define IMX8QM_EMMC0_CLK_CONN_EMMC0_CLK IMX8QM_EMMC0_CLK 0 788*4882a593Smuzhiyun #define IMX8QM_EMMC0_CLK_CONN_NAND_READY_B IMX8QM_EMMC0_CLK 1 789*4882a593Smuzhiyun #define IMX8QM_EMMC0_CMD_CONN_EMMC0_CMD IMX8QM_EMMC0_CMD 0 790*4882a593Smuzhiyun #define IMX8QM_EMMC0_CMD_CONN_NAND_DQS IMX8QM_EMMC0_CMD 1 791*4882a593Smuzhiyun #define IMX8QM_EMMC0_CMD_AUD_MQS_R IMX8QM_EMMC0_CMD 2 792*4882a593Smuzhiyun #define IMX8QM_EMMC0_CMD_LSIO_GPIO5_IO03 IMX8QM_EMMC0_CMD 3 793*4882a593Smuzhiyun #define IMX8QM_EMMC0_DATA0_CONN_EMMC0_DATA0 IMX8QM_EMMC0_DATA0 0 794*4882a593Smuzhiyun #define IMX8QM_EMMC0_DATA0_CONN_NAND_DATA00 IMX8QM_EMMC0_DATA0 1 795*4882a593Smuzhiyun #define IMX8QM_EMMC0_DATA0_LSIO_GPIO5_IO04 IMX8QM_EMMC0_DATA0 3 796*4882a593Smuzhiyun #define IMX8QM_EMMC0_DATA1_CONN_EMMC0_DATA1 IMX8QM_EMMC0_DATA1 0 797*4882a593Smuzhiyun #define IMX8QM_EMMC0_DATA1_CONN_NAND_DATA01 IMX8QM_EMMC0_DATA1 1 798*4882a593Smuzhiyun #define IMX8QM_EMMC0_DATA1_LSIO_GPIO5_IO05 IMX8QM_EMMC0_DATA1 3 799*4882a593Smuzhiyun #define IMX8QM_EMMC0_DATA2_CONN_EMMC0_DATA2 IMX8QM_EMMC0_DATA2 0 800*4882a593Smuzhiyun #define IMX8QM_EMMC0_DATA2_CONN_NAND_DATA02 IMX8QM_EMMC0_DATA2 1 801*4882a593Smuzhiyun #define IMX8QM_EMMC0_DATA2_LSIO_GPIO5_IO06 IMX8QM_EMMC0_DATA2 3 802*4882a593Smuzhiyun #define IMX8QM_EMMC0_DATA3_CONN_EMMC0_DATA3 IMX8QM_EMMC0_DATA3 0 803*4882a593Smuzhiyun #define IMX8QM_EMMC0_DATA3_CONN_NAND_DATA03 IMX8QM_EMMC0_DATA3 1 804*4882a593Smuzhiyun #define IMX8QM_EMMC0_DATA3_LSIO_GPIO5_IO07 IMX8QM_EMMC0_DATA3 3 805*4882a593Smuzhiyun #define IMX8QM_EMMC0_DATA4_CONN_EMMC0_DATA4 IMX8QM_EMMC0_DATA4 0 806*4882a593Smuzhiyun #define IMX8QM_EMMC0_DATA4_CONN_NAND_DATA04 IMX8QM_EMMC0_DATA4 1 807*4882a593Smuzhiyun #define IMX8QM_EMMC0_DATA4_LSIO_GPIO5_IO08 IMX8QM_EMMC0_DATA4 3 808*4882a593Smuzhiyun #define IMX8QM_EMMC0_DATA5_CONN_EMMC0_DATA5 IMX8QM_EMMC0_DATA5 0 809*4882a593Smuzhiyun #define IMX8QM_EMMC0_DATA5_CONN_NAND_DATA05 IMX8QM_EMMC0_DATA5 1 810*4882a593Smuzhiyun #define IMX8QM_EMMC0_DATA5_LSIO_GPIO5_IO09 IMX8QM_EMMC0_DATA5 3 811*4882a593Smuzhiyun #define IMX8QM_EMMC0_DATA6_CONN_EMMC0_DATA6 IMX8QM_EMMC0_DATA6 0 812*4882a593Smuzhiyun #define IMX8QM_EMMC0_DATA6_CONN_NAND_DATA06 IMX8QM_EMMC0_DATA6 1 813*4882a593Smuzhiyun #define IMX8QM_EMMC0_DATA6_LSIO_GPIO5_IO10 IMX8QM_EMMC0_DATA6 3 814*4882a593Smuzhiyun #define IMX8QM_EMMC0_DATA7_CONN_EMMC0_DATA7 IMX8QM_EMMC0_DATA7 0 815*4882a593Smuzhiyun #define IMX8QM_EMMC0_DATA7_CONN_NAND_DATA07 IMX8QM_EMMC0_DATA7 1 816*4882a593Smuzhiyun #define IMX8QM_EMMC0_DATA7_LSIO_GPIO5_IO11 IMX8QM_EMMC0_DATA7 3 817*4882a593Smuzhiyun #define IMX8QM_EMMC0_STROBE_CONN_EMMC0_STROBE IMX8QM_EMMC0_STROBE 0 818*4882a593Smuzhiyun #define IMX8QM_EMMC0_STROBE_CONN_NAND_CLE IMX8QM_EMMC0_STROBE 1 819*4882a593Smuzhiyun #define IMX8QM_EMMC0_STROBE_LSIO_GPIO5_IO12 IMX8QM_EMMC0_STROBE 3 820*4882a593Smuzhiyun #define IMX8QM_EMMC0_RESET_B_CONN_EMMC0_RESET_B IMX8QM_EMMC0_RESET_B 0 821*4882a593Smuzhiyun #define IMX8QM_EMMC0_RESET_B_CONN_NAND_WP_B IMX8QM_EMMC0_RESET_B 1 822*4882a593Smuzhiyun #define IMX8QM_EMMC0_RESET_B_CONN_USDHC1_VSELECT IMX8QM_EMMC0_RESET_B 2 823*4882a593Smuzhiyun #define IMX8QM_EMMC0_RESET_B_LSIO_GPIO5_IO13 IMX8QM_EMMC0_RESET_B 3 824*4882a593Smuzhiyun #define IMX8QM_USDHC1_CLK_CONN_USDHC1_CLK IMX8QM_USDHC1_CLK 0 825*4882a593Smuzhiyun #define IMX8QM_USDHC1_CLK_AUD_MQS_R IMX8QM_USDHC1_CLK 1 826*4882a593Smuzhiyun #define IMX8QM_USDHC1_CMD_CONN_USDHC1_CMD IMX8QM_USDHC1_CMD 0 827*4882a593Smuzhiyun #define IMX8QM_USDHC1_CMD_AUD_MQS_L IMX8QM_USDHC1_CMD 1 828*4882a593Smuzhiyun #define IMX8QM_USDHC1_CMD_LSIO_GPIO5_IO14 IMX8QM_USDHC1_CMD 3 829*4882a593Smuzhiyun #define IMX8QM_USDHC1_DATA0_CONN_USDHC1_DATA0 IMX8QM_USDHC1_DATA0 0 830*4882a593Smuzhiyun #define IMX8QM_USDHC1_DATA0_CONN_NAND_RE_N IMX8QM_USDHC1_DATA0 1 831*4882a593Smuzhiyun #define IMX8QM_USDHC1_DATA0_LSIO_GPIO5_IO15 IMX8QM_USDHC1_DATA0 3 832*4882a593Smuzhiyun #define IMX8QM_USDHC1_DATA1_CONN_USDHC1_DATA1 IMX8QM_USDHC1_DATA1 0 833*4882a593Smuzhiyun #define IMX8QM_USDHC1_DATA1_CONN_NAND_RE_P IMX8QM_USDHC1_DATA1 1 834*4882a593Smuzhiyun #define IMX8QM_USDHC1_DATA1_LSIO_GPIO5_IO16 IMX8QM_USDHC1_DATA1 3 835*4882a593Smuzhiyun #define IMX8QM_USDHC1_DATA2_CONN_USDHC1_DATA2 IMX8QM_USDHC1_DATA2 0 836*4882a593Smuzhiyun #define IMX8QM_USDHC1_DATA2_CONN_NAND_DQS_N IMX8QM_USDHC1_DATA2 1 837*4882a593Smuzhiyun #define IMX8QM_USDHC1_DATA2_LSIO_GPIO5_IO17 IMX8QM_USDHC1_DATA2 3 838*4882a593Smuzhiyun #define IMX8QM_USDHC1_DATA3_CONN_USDHC1_DATA3 IMX8QM_USDHC1_DATA3 0 839*4882a593Smuzhiyun #define IMX8QM_USDHC1_DATA3_CONN_NAND_DQS_P IMX8QM_USDHC1_DATA3 1 840*4882a593Smuzhiyun #define IMX8QM_USDHC1_DATA3_LSIO_GPIO5_IO18 IMX8QM_USDHC1_DATA3 3 841*4882a593Smuzhiyun #define IMX8QM_USDHC1_DATA4_CONN_USDHC1_DATA4 IMX8QM_USDHC1_DATA4 0 842*4882a593Smuzhiyun #define IMX8QM_USDHC1_DATA4_CONN_NAND_CE0_B IMX8QM_USDHC1_DATA4 1 843*4882a593Smuzhiyun #define IMX8QM_USDHC1_DATA4_AUD_MQS_R IMX8QM_USDHC1_DATA4 2 844*4882a593Smuzhiyun #define IMX8QM_USDHC1_DATA4_LSIO_GPIO5_IO19 IMX8QM_USDHC1_DATA4 3 845*4882a593Smuzhiyun #define IMX8QM_USDHC1_DATA5_CONN_USDHC1_DATA5 IMX8QM_USDHC1_DATA5 0 846*4882a593Smuzhiyun #define IMX8QM_USDHC1_DATA5_CONN_NAND_RE_B IMX8QM_USDHC1_DATA5 1 847*4882a593Smuzhiyun #define IMX8QM_USDHC1_DATA5_AUD_MQS_L IMX8QM_USDHC1_DATA5 2 848*4882a593Smuzhiyun #define IMX8QM_USDHC1_DATA5_LSIO_GPIO5_IO20 IMX8QM_USDHC1_DATA5 3 849*4882a593Smuzhiyun #define IMX8QM_USDHC1_DATA6_CONN_USDHC1_DATA6 IMX8QM_USDHC1_DATA6 0 850*4882a593Smuzhiyun #define IMX8QM_USDHC1_DATA6_CONN_NAND_WE_B IMX8QM_USDHC1_DATA6 1 851*4882a593Smuzhiyun #define IMX8QM_USDHC1_DATA6_CONN_USDHC1_WP IMX8QM_USDHC1_DATA6 2 852*4882a593Smuzhiyun #define IMX8QM_USDHC1_DATA6_LSIO_GPIO5_IO21 IMX8QM_USDHC1_DATA6 3 853*4882a593Smuzhiyun #define IMX8QM_USDHC1_DATA7_CONN_USDHC1_DATA7 IMX8QM_USDHC1_DATA7 0 854*4882a593Smuzhiyun #define IMX8QM_USDHC1_DATA7_CONN_NAND_ALE IMX8QM_USDHC1_DATA7 1 855*4882a593Smuzhiyun #define IMX8QM_USDHC1_DATA7_CONN_USDHC1_CD_B IMX8QM_USDHC1_DATA7 2 856*4882a593Smuzhiyun #define IMX8QM_USDHC1_DATA7_LSIO_GPIO5_IO22 IMX8QM_USDHC1_DATA7 3 857*4882a593Smuzhiyun #define IMX8QM_USDHC1_STROBE_CONN_USDHC1_STROBE IMX8QM_USDHC1_STROBE 0 858*4882a593Smuzhiyun #define IMX8QM_USDHC1_STROBE_CONN_NAND_CE1_B IMX8QM_USDHC1_STROBE 1 859*4882a593Smuzhiyun #define IMX8QM_USDHC1_STROBE_CONN_USDHC1_RESET_B IMX8QM_USDHC1_STROBE 2 860*4882a593Smuzhiyun #define IMX8QM_USDHC1_STROBE_LSIO_GPIO5_IO23 IMX8QM_USDHC1_STROBE 3 861*4882a593Smuzhiyun #define IMX8QM_USDHC2_CLK_CONN_USDHC2_CLK IMX8QM_USDHC2_CLK 0 862*4882a593Smuzhiyun #define IMX8QM_USDHC2_CLK_AUD_MQS_R IMX8QM_USDHC2_CLK 1 863*4882a593Smuzhiyun #define IMX8QM_USDHC2_CLK_LSIO_GPIO5_IO24 IMX8QM_USDHC2_CLK 3 864*4882a593Smuzhiyun #define IMX8QM_USDHC2_CMD_CONN_USDHC2_CMD IMX8QM_USDHC2_CMD 0 865*4882a593Smuzhiyun #define IMX8QM_USDHC2_CMD_AUD_MQS_L IMX8QM_USDHC2_CMD 1 866*4882a593Smuzhiyun #define IMX8QM_USDHC2_CMD_LSIO_GPIO5_IO25 IMX8QM_USDHC2_CMD 3 867*4882a593Smuzhiyun #define IMX8QM_USDHC2_DATA0_CONN_USDHC2_DATA0 IMX8QM_USDHC2_DATA0 0 868*4882a593Smuzhiyun #define IMX8QM_USDHC2_DATA0_DMA_UART4_RX IMX8QM_USDHC2_DATA0 1 869*4882a593Smuzhiyun #define IMX8QM_USDHC2_DATA0_LSIO_GPIO5_IO26 IMX8QM_USDHC2_DATA0 3 870*4882a593Smuzhiyun #define IMX8QM_USDHC2_DATA1_CONN_USDHC2_DATA1 IMX8QM_USDHC2_DATA1 0 871*4882a593Smuzhiyun #define IMX8QM_USDHC2_DATA1_DMA_UART4_TX IMX8QM_USDHC2_DATA1 1 872*4882a593Smuzhiyun #define IMX8QM_USDHC2_DATA1_LSIO_GPIO5_IO27 IMX8QM_USDHC2_DATA1 3 873*4882a593Smuzhiyun #define IMX8QM_USDHC2_DATA2_CONN_USDHC2_DATA2 IMX8QM_USDHC2_DATA2 0 874*4882a593Smuzhiyun #define IMX8QM_USDHC2_DATA2_DMA_UART4_CTS_B IMX8QM_USDHC2_DATA2 1 875*4882a593Smuzhiyun #define IMX8QM_USDHC2_DATA2_LSIO_GPIO5_IO28 IMX8QM_USDHC2_DATA2 3 876*4882a593Smuzhiyun #define IMX8QM_USDHC2_DATA3_CONN_USDHC2_DATA3 IMX8QM_USDHC2_DATA3 0 877*4882a593Smuzhiyun #define IMX8QM_USDHC2_DATA3_DMA_UART4_RTS_B IMX8QM_USDHC2_DATA3 1 878*4882a593Smuzhiyun #define IMX8QM_USDHC2_DATA3_LSIO_GPIO5_IO29 IMX8QM_USDHC2_DATA3 3 879*4882a593Smuzhiyun #define IMX8QM_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC IMX8QM_ENET0_RGMII_TXC 0 880*4882a593Smuzhiyun #define IMX8QM_ENET0_RGMII_TXC_CONN_ENET0_RCLK50M_OUT IMX8QM_ENET0_RGMII_TXC 1 881*4882a593Smuzhiyun #define IMX8QM_ENET0_RGMII_TXC_CONN_ENET0_RCLK50M_IN IMX8QM_ENET0_RGMII_TXC 2 882*4882a593Smuzhiyun #define IMX8QM_ENET0_RGMII_TXC_LSIO_GPIO5_IO30 IMX8QM_ENET0_RGMII_TXC 3 883*4882a593Smuzhiyun #define IMX8QM_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL IMX8QM_ENET0_RGMII_TX_CTL 0 884*4882a593Smuzhiyun #define IMX8QM_ENET0_RGMII_TX_CTL_LSIO_GPIO5_IO31 IMX8QM_ENET0_RGMII_TX_CTL 3 885*4882a593Smuzhiyun #define IMX8QM_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 IMX8QM_ENET0_RGMII_TXD0 0 886*4882a593Smuzhiyun #define IMX8QM_ENET0_RGMII_TXD0_LSIO_GPIO6_IO00 IMX8QM_ENET0_RGMII_TXD0 3 887*4882a593Smuzhiyun #define IMX8QM_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 IMX8QM_ENET0_RGMII_TXD1 0 888*4882a593Smuzhiyun #define IMX8QM_ENET0_RGMII_TXD1_LSIO_GPIO6_IO01 IMX8QM_ENET0_RGMII_TXD1 3 889*4882a593Smuzhiyun #define IMX8QM_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 IMX8QM_ENET0_RGMII_TXD2 0 890*4882a593Smuzhiyun #define IMX8QM_ENET0_RGMII_TXD2_DMA_UART3_TX IMX8QM_ENET0_RGMII_TXD2 1 891*4882a593Smuzhiyun #define IMX8QM_ENET0_RGMII_TXD2_VPU_TSI_S1_VID IMX8QM_ENET0_RGMII_TXD2 2 892*4882a593Smuzhiyun #define IMX8QM_ENET0_RGMII_TXD2_LSIO_GPIO6_IO02 IMX8QM_ENET0_RGMII_TXD2 3 893*4882a593Smuzhiyun #define IMX8QM_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 IMX8QM_ENET0_RGMII_TXD3 0 894*4882a593Smuzhiyun #define IMX8QM_ENET0_RGMII_TXD3_DMA_UART3_RTS_B IMX8QM_ENET0_RGMII_TXD3 1 895*4882a593Smuzhiyun #define IMX8QM_ENET0_RGMII_TXD3_VPU_TSI_S1_SYNC IMX8QM_ENET0_RGMII_TXD3 2 896*4882a593Smuzhiyun #define IMX8QM_ENET0_RGMII_TXD3_LSIO_GPIO6_IO03 IMX8QM_ENET0_RGMII_TXD3 3 897*4882a593Smuzhiyun #define IMX8QM_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC IMX8QM_ENET0_RGMII_RXC 0 898*4882a593Smuzhiyun #define IMX8QM_ENET0_RGMII_RXC_DMA_UART3_CTS_B IMX8QM_ENET0_RGMII_RXC 1 899*4882a593Smuzhiyun #define IMX8QM_ENET0_RGMII_RXC_VPU_TSI_S1_DATA IMX8QM_ENET0_RGMII_RXC 2 900*4882a593Smuzhiyun #define IMX8QM_ENET0_RGMII_RXC_LSIO_GPIO6_IO04 IMX8QM_ENET0_RGMII_RXC 3 901*4882a593Smuzhiyun #define IMX8QM_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL IMX8QM_ENET0_RGMII_RX_CTL 0 902*4882a593Smuzhiyun #define IMX8QM_ENET0_RGMII_RX_CTL_VPU_TSI_S0_VID IMX8QM_ENET0_RGMII_RX_CTL 2 903*4882a593Smuzhiyun #define IMX8QM_ENET0_RGMII_RX_CTL_LSIO_GPIO6_IO05 IMX8QM_ENET0_RGMII_RX_CTL 3 904*4882a593Smuzhiyun #define IMX8QM_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 IMX8QM_ENET0_RGMII_RXD0 0 905*4882a593Smuzhiyun #define IMX8QM_ENET0_RGMII_RXD0_VPU_TSI_S0_SYNC IMX8QM_ENET0_RGMII_RXD0 2 906*4882a593Smuzhiyun #define IMX8QM_ENET0_RGMII_RXD0_LSIO_GPIO6_IO06 IMX8QM_ENET0_RGMII_RXD0 3 907*4882a593Smuzhiyun #define IMX8QM_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 IMX8QM_ENET0_RGMII_RXD1 0 908*4882a593Smuzhiyun #define IMX8QM_ENET0_RGMII_RXD1_VPU_TSI_S0_DATA IMX8QM_ENET0_RGMII_RXD1 2 909*4882a593Smuzhiyun #define IMX8QM_ENET0_RGMII_RXD1_LSIO_GPIO6_IO07 IMX8QM_ENET0_RGMII_RXD1 3 910*4882a593Smuzhiyun #define IMX8QM_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 IMX8QM_ENET0_RGMII_RXD2 0 911*4882a593Smuzhiyun #define IMX8QM_ENET0_RGMII_RXD2_CONN_ENET0_RMII_RX_ER IMX8QM_ENET0_RGMII_RXD2 1 912*4882a593Smuzhiyun #define IMX8QM_ENET0_RGMII_RXD2_VPU_TSI_S0_CLK IMX8QM_ENET0_RGMII_RXD2 2 913*4882a593Smuzhiyun #define IMX8QM_ENET0_RGMII_RXD2_LSIO_GPIO6_IO08 IMX8QM_ENET0_RGMII_RXD2 3 914*4882a593Smuzhiyun #define IMX8QM_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 IMX8QM_ENET0_RGMII_RXD3 0 915*4882a593Smuzhiyun #define IMX8QM_ENET0_RGMII_RXD3_DMA_UART3_RX IMX8QM_ENET0_RGMII_RXD3 1 916*4882a593Smuzhiyun #define IMX8QM_ENET0_RGMII_RXD3_VPU_TSI_S1_CLK IMX8QM_ENET0_RGMII_RXD3 2 917*4882a593Smuzhiyun #define IMX8QM_ENET0_RGMII_RXD3_LSIO_GPIO6_IO09 IMX8QM_ENET0_RGMII_RXD3 3 918*4882a593Smuzhiyun #define IMX8QM_ENET1_RGMII_TXC_CONN_ENET1_RGMII_TXC IMX8QM_ENET1_RGMII_TXC 0 919*4882a593Smuzhiyun #define IMX8QM_ENET1_RGMII_TXC_CONN_ENET1_RCLK50M_OUT IMX8QM_ENET1_RGMII_TXC 1 920*4882a593Smuzhiyun #define IMX8QM_ENET1_RGMII_TXC_CONN_ENET1_RCLK50M_IN IMX8QM_ENET1_RGMII_TXC 2 921*4882a593Smuzhiyun #define IMX8QM_ENET1_RGMII_TXC_LSIO_GPIO6_IO10 IMX8QM_ENET1_RGMII_TXC 3 922*4882a593Smuzhiyun #define IMX8QM_ENET1_RGMII_TX_CTL_CONN_ENET1_RGMII_TX_CTL IMX8QM_ENET1_RGMII_TX_CTL 0 923*4882a593Smuzhiyun #define IMX8QM_ENET1_RGMII_TX_CTL_LSIO_GPIO6_IO11 IMX8QM_ENET1_RGMII_TX_CTL 3 924*4882a593Smuzhiyun #define IMX8QM_ENET1_RGMII_TXD0_CONN_ENET1_RGMII_TXD0 IMX8QM_ENET1_RGMII_TXD0 0 925*4882a593Smuzhiyun #define IMX8QM_ENET1_RGMII_TXD0_LSIO_GPIO6_IO12 IMX8QM_ENET1_RGMII_TXD0 3 926*4882a593Smuzhiyun #define IMX8QM_ENET1_RGMII_TXD1_CONN_ENET1_RGMII_TXD1 IMX8QM_ENET1_RGMII_TXD1 0 927*4882a593Smuzhiyun #define IMX8QM_ENET1_RGMII_TXD1_LSIO_GPIO6_IO13 IMX8QM_ENET1_RGMII_TXD1 3 928*4882a593Smuzhiyun #define IMX8QM_ENET1_RGMII_TXD2_CONN_ENET1_RGMII_TXD2 IMX8QM_ENET1_RGMII_TXD2 0 929*4882a593Smuzhiyun #define IMX8QM_ENET1_RGMII_TXD2_DMA_UART3_TX IMX8QM_ENET1_RGMII_TXD2 1 930*4882a593Smuzhiyun #define IMX8QM_ENET1_RGMII_TXD2_VPU_TSI_S1_VID IMX8QM_ENET1_RGMII_TXD2 2 931*4882a593Smuzhiyun #define IMX8QM_ENET1_RGMII_TXD2_LSIO_GPIO6_IO14 IMX8QM_ENET1_RGMII_TXD2 3 932*4882a593Smuzhiyun #define IMX8QM_ENET1_RGMII_TXD3_CONN_ENET1_RGMII_TXD3 IMX8QM_ENET1_RGMII_TXD3 0 933*4882a593Smuzhiyun #define IMX8QM_ENET1_RGMII_TXD3_DMA_UART3_RTS_B IMX8QM_ENET1_RGMII_TXD3 1 934*4882a593Smuzhiyun #define IMX8QM_ENET1_RGMII_TXD3_VPU_TSI_S1_SYNC IMX8QM_ENET1_RGMII_TXD3 2 935*4882a593Smuzhiyun #define IMX8QM_ENET1_RGMII_TXD3_LSIO_GPIO6_IO15 IMX8QM_ENET1_RGMII_TXD3 3 936*4882a593Smuzhiyun #define IMX8QM_ENET1_RGMII_RXC_CONN_ENET1_RGMII_RXC IMX8QM_ENET1_RGMII_RXC 0 937*4882a593Smuzhiyun #define IMX8QM_ENET1_RGMII_RXC_DMA_UART3_CTS_B IMX8QM_ENET1_RGMII_RXC 1 938*4882a593Smuzhiyun #define IMX8QM_ENET1_RGMII_RXC_VPU_TSI_S1_DATA IMX8QM_ENET1_RGMII_RXC 2 939*4882a593Smuzhiyun #define IMX8QM_ENET1_RGMII_RXC_LSIO_GPIO6_IO16 IMX8QM_ENET1_RGMII_RXC 3 940*4882a593Smuzhiyun #define IMX8QM_ENET1_RGMII_RX_CTL_CONN_ENET1_RGMII_RX_CTL IMX8QM_ENET1_RGMII_RX_CTL 0 941*4882a593Smuzhiyun #define IMX8QM_ENET1_RGMII_RX_CTL_VPU_TSI_S0_VID IMX8QM_ENET1_RGMII_RX_CTL 2 942*4882a593Smuzhiyun #define IMX8QM_ENET1_RGMII_RX_CTL_LSIO_GPIO6_IO17 IMX8QM_ENET1_RGMII_RX_CTL 3 943*4882a593Smuzhiyun #define IMX8QM_ENET1_RGMII_RXD0_CONN_ENET1_RGMII_RXD0 IMX8QM_ENET1_RGMII_RXD0 0 944*4882a593Smuzhiyun #define IMX8QM_ENET1_RGMII_RXD0_VPU_TSI_S0_SYNC IMX8QM_ENET1_RGMII_RXD0 2 945*4882a593Smuzhiyun #define IMX8QM_ENET1_RGMII_RXD0_LSIO_GPIO6_IO18 IMX8QM_ENET1_RGMII_RXD0 3 946*4882a593Smuzhiyun #define IMX8QM_ENET1_RGMII_RXD1_CONN_ENET1_RGMII_RXD1 IMX8QM_ENET1_RGMII_RXD1 0 947*4882a593Smuzhiyun #define IMX8QM_ENET1_RGMII_RXD1_VPU_TSI_S0_DATA IMX8QM_ENET1_RGMII_RXD1 2 948*4882a593Smuzhiyun #define IMX8QM_ENET1_RGMII_RXD1_LSIO_GPIO6_IO19 IMX8QM_ENET1_RGMII_RXD1 3 949*4882a593Smuzhiyun #define IMX8QM_ENET1_RGMII_RXD2_CONN_ENET1_RGMII_RXD2 IMX8QM_ENET1_RGMII_RXD2 0 950*4882a593Smuzhiyun #define IMX8QM_ENET1_RGMII_RXD2_CONN_ENET1_RMII_RX_ER IMX8QM_ENET1_RGMII_RXD2 1 951*4882a593Smuzhiyun #define IMX8QM_ENET1_RGMII_RXD2_VPU_TSI_S0_CLK IMX8QM_ENET1_RGMII_RXD2 2 952*4882a593Smuzhiyun #define IMX8QM_ENET1_RGMII_RXD2_LSIO_GPIO6_IO20 IMX8QM_ENET1_RGMII_RXD2 3 953*4882a593Smuzhiyun #define IMX8QM_ENET1_RGMII_RXD3_CONN_ENET1_RGMII_RXD3 IMX8QM_ENET1_RGMII_RXD3 0 954*4882a593Smuzhiyun #define IMX8QM_ENET1_RGMII_RXD3_DMA_UART3_RX IMX8QM_ENET1_RGMII_RXD3 1 955*4882a593Smuzhiyun #define IMX8QM_ENET1_RGMII_RXD3_VPU_TSI_S1_CLK IMX8QM_ENET1_RGMII_RXD3 2 956*4882a593Smuzhiyun #define IMX8QM_ENET1_RGMII_RXD3_LSIO_GPIO6_IO21 IMX8QM_ENET1_RGMII_RXD3 3 957*4882a593Smuzhiyun #define IMX8QM_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB_PAD IMX8QM_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB 0 958*4882a593Smuzhiyun #define IMX8QM_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA_PAD IMX8QM_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA 0 959*4882a593Smuzhiyun 960*4882a593Smuzhiyun #endif /* _IMX8QM_PADS_H */ 961