1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (c) 2014 MediaTek Inc. 4*4882a593Smuzhiyun * Author: Hongzhou.Yang <hongzhou.yang@mediatek.com> 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #ifndef _DT_BINDINGS_PINCTRL_MT65XX_H 8*4882a593Smuzhiyun #define _DT_BINDINGS_PINCTRL_MT65XX_H 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #define MTK_PIN_NO(x) ((x) << 8) 11*4882a593Smuzhiyun #define MTK_GET_PIN_NO(x) ((x) >> 8) 12*4882a593Smuzhiyun #define MTK_GET_PIN_FUNC(x) ((x) & 0xf) 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun #define MTK_PUPD_SET_R1R0_00 100 15*4882a593Smuzhiyun #define MTK_PUPD_SET_R1R0_01 101 16*4882a593Smuzhiyun #define MTK_PUPD_SET_R1R0_10 102 17*4882a593Smuzhiyun #define MTK_PUPD_SET_R1R0_11 103 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun #define MTK_DRIVE_2mA 2 20*4882a593Smuzhiyun #define MTK_DRIVE_4mA 4 21*4882a593Smuzhiyun #define MTK_DRIVE_6mA 6 22*4882a593Smuzhiyun #define MTK_DRIVE_8mA 8 23*4882a593Smuzhiyun #define MTK_DRIVE_10mA 10 24*4882a593Smuzhiyun #define MTK_DRIVE_12mA 12 25*4882a593Smuzhiyun #define MTK_DRIVE_14mA 14 26*4882a593Smuzhiyun #define MTK_DRIVE_16mA 16 27*4882a593Smuzhiyun #define MTK_DRIVE_20mA 20 28*4882a593Smuzhiyun #define MTK_DRIVE_24mA 24 29*4882a593Smuzhiyun #define MTK_DRIVE_28mA 28 30*4882a593Smuzhiyun #define MTK_DRIVE_32mA 32 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun #endif /* _DT_BINDINGS_PINCTRL_MT65XX_H */ 33