1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Device Tree defines for Lochnagar pinctrl 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (c) 2018 Cirrus Logic, Inc. and 6*4882a593Smuzhiyun * Cirrus Logic International Semiconductor Ltd. 7*4882a593Smuzhiyun * 8*4882a593Smuzhiyun * Author: Charles Keepax <ckeepax@opensource.cirrus.com> 9*4882a593Smuzhiyun */ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #ifndef DT_BINDINGS_PINCTRL_LOCHNAGAR_H 12*4882a593Smuzhiyun #define DT_BINDINGS_PINCTRL_LOCHNAGAR_H 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun #define LOCHNAGAR1_PIN_CDC_RESET 0 15*4882a593Smuzhiyun #define LOCHNAGAR1_PIN_DSP_RESET 1 16*4882a593Smuzhiyun #define LOCHNAGAR1_PIN_CDC_CIF1MODE 2 17*4882a593Smuzhiyun #define LOCHNAGAR1_PIN_NUM_GPIOS 3 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun #define LOCHNAGAR2_PIN_CDC_RESET 0 20*4882a593Smuzhiyun #define LOCHNAGAR2_PIN_DSP_RESET 1 21*4882a593Smuzhiyun #define LOCHNAGAR2_PIN_CDC_CIF1MODE 2 22*4882a593Smuzhiyun #define LOCHNAGAR2_PIN_CDC_LDOENA 3 23*4882a593Smuzhiyun #define LOCHNAGAR2_PIN_SPDIF_HWMODE 4 24*4882a593Smuzhiyun #define LOCHNAGAR2_PIN_SPDIF_RESET 5 25*4882a593Smuzhiyun #define LOCHNAGAR2_PIN_FPGA_GPIO1 6 26*4882a593Smuzhiyun #define LOCHNAGAR2_PIN_FPGA_GPIO2 7 27*4882a593Smuzhiyun #define LOCHNAGAR2_PIN_FPGA_GPIO3 8 28*4882a593Smuzhiyun #define LOCHNAGAR2_PIN_FPGA_GPIO4 9 29*4882a593Smuzhiyun #define LOCHNAGAR2_PIN_FPGA_GPIO5 10 30*4882a593Smuzhiyun #define LOCHNAGAR2_PIN_FPGA_GPIO6 11 31*4882a593Smuzhiyun #define LOCHNAGAR2_PIN_CDC_GPIO1 12 32*4882a593Smuzhiyun #define LOCHNAGAR2_PIN_CDC_GPIO2 13 33*4882a593Smuzhiyun #define LOCHNAGAR2_PIN_CDC_GPIO3 14 34*4882a593Smuzhiyun #define LOCHNAGAR2_PIN_CDC_GPIO4 15 35*4882a593Smuzhiyun #define LOCHNAGAR2_PIN_CDC_GPIO5 16 36*4882a593Smuzhiyun #define LOCHNAGAR2_PIN_CDC_GPIO6 17 37*4882a593Smuzhiyun #define LOCHNAGAR2_PIN_CDC_GPIO7 18 38*4882a593Smuzhiyun #define LOCHNAGAR2_PIN_CDC_GPIO8 19 39*4882a593Smuzhiyun #define LOCHNAGAR2_PIN_DSP_GPIO1 20 40*4882a593Smuzhiyun #define LOCHNAGAR2_PIN_DSP_GPIO2 21 41*4882a593Smuzhiyun #define LOCHNAGAR2_PIN_DSP_GPIO3 22 42*4882a593Smuzhiyun #define LOCHNAGAR2_PIN_DSP_GPIO4 23 43*4882a593Smuzhiyun #define LOCHNAGAR2_PIN_DSP_GPIO5 24 44*4882a593Smuzhiyun #define LOCHNAGAR2_PIN_DSP_GPIO6 25 45*4882a593Smuzhiyun #define LOCHNAGAR2_PIN_GF_GPIO2 26 46*4882a593Smuzhiyun #define LOCHNAGAR2_PIN_GF_GPIO3 27 47*4882a593Smuzhiyun #define LOCHNAGAR2_PIN_GF_GPIO7 28 48*4882a593Smuzhiyun #define LOCHNAGAR2_PIN_CDC_AIF1_BCLK 29 49*4882a593Smuzhiyun #define LOCHNAGAR2_PIN_CDC_AIF1_RXDAT 30 50*4882a593Smuzhiyun #define LOCHNAGAR2_PIN_CDC_AIF1_LRCLK 31 51*4882a593Smuzhiyun #define LOCHNAGAR2_PIN_CDC_AIF1_TXDAT 32 52*4882a593Smuzhiyun #define LOCHNAGAR2_PIN_CDC_AIF2_BCLK 33 53*4882a593Smuzhiyun #define LOCHNAGAR2_PIN_CDC_AIF2_RXDAT 34 54*4882a593Smuzhiyun #define LOCHNAGAR2_PIN_CDC_AIF2_LRCLK 35 55*4882a593Smuzhiyun #define LOCHNAGAR2_PIN_CDC_AIF2_TXDAT 36 56*4882a593Smuzhiyun #define LOCHNAGAR2_PIN_CDC_AIF3_BCLK 37 57*4882a593Smuzhiyun #define LOCHNAGAR2_PIN_CDC_AIF3_RXDAT 38 58*4882a593Smuzhiyun #define LOCHNAGAR2_PIN_CDC_AIF3_LRCLK 39 59*4882a593Smuzhiyun #define LOCHNAGAR2_PIN_CDC_AIF3_TXDAT 40 60*4882a593Smuzhiyun #define LOCHNAGAR2_PIN_DSP_AIF1_BCLK 41 61*4882a593Smuzhiyun #define LOCHNAGAR2_PIN_DSP_AIF1_RXDAT 42 62*4882a593Smuzhiyun #define LOCHNAGAR2_PIN_DSP_AIF1_LRCLK 43 63*4882a593Smuzhiyun #define LOCHNAGAR2_PIN_DSP_AIF1_TXDAT 44 64*4882a593Smuzhiyun #define LOCHNAGAR2_PIN_DSP_AIF2_BCLK 45 65*4882a593Smuzhiyun #define LOCHNAGAR2_PIN_DSP_AIF2_RXDAT 46 66*4882a593Smuzhiyun #define LOCHNAGAR2_PIN_DSP_AIF2_LRCLK 47 67*4882a593Smuzhiyun #define LOCHNAGAR2_PIN_DSP_AIF2_TXDAT 48 68*4882a593Smuzhiyun #define LOCHNAGAR2_PIN_PSIA1_BCLK 49 69*4882a593Smuzhiyun #define LOCHNAGAR2_PIN_PSIA1_RXDAT 50 70*4882a593Smuzhiyun #define LOCHNAGAR2_PIN_PSIA1_LRCLK 51 71*4882a593Smuzhiyun #define LOCHNAGAR2_PIN_PSIA1_TXDAT 52 72*4882a593Smuzhiyun #define LOCHNAGAR2_PIN_PSIA2_BCLK 53 73*4882a593Smuzhiyun #define LOCHNAGAR2_PIN_PSIA2_RXDAT 54 74*4882a593Smuzhiyun #define LOCHNAGAR2_PIN_PSIA2_LRCLK 55 75*4882a593Smuzhiyun #define LOCHNAGAR2_PIN_PSIA2_TXDAT 56 76*4882a593Smuzhiyun #define LOCHNAGAR2_PIN_GF_AIF3_BCLK 57 77*4882a593Smuzhiyun #define LOCHNAGAR2_PIN_GF_AIF3_RXDAT 58 78*4882a593Smuzhiyun #define LOCHNAGAR2_PIN_GF_AIF3_LRCLK 59 79*4882a593Smuzhiyun #define LOCHNAGAR2_PIN_GF_AIF3_TXDAT 60 80*4882a593Smuzhiyun #define LOCHNAGAR2_PIN_GF_AIF4_BCLK 61 81*4882a593Smuzhiyun #define LOCHNAGAR2_PIN_GF_AIF4_RXDAT 62 82*4882a593Smuzhiyun #define LOCHNAGAR2_PIN_GF_AIF4_LRCLK 63 83*4882a593Smuzhiyun #define LOCHNAGAR2_PIN_GF_AIF4_TXDAT 64 84*4882a593Smuzhiyun #define LOCHNAGAR2_PIN_GF_AIF1_BCLK 65 85*4882a593Smuzhiyun #define LOCHNAGAR2_PIN_GF_AIF1_RXDAT 66 86*4882a593Smuzhiyun #define LOCHNAGAR2_PIN_GF_AIF1_LRCLK 67 87*4882a593Smuzhiyun #define LOCHNAGAR2_PIN_GF_AIF1_TXDAT 68 88*4882a593Smuzhiyun #define LOCHNAGAR2_PIN_GF_AIF2_BCLK 69 89*4882a593Smuzhiyun #define LOCHNAGAR2_PIN_GF_AIF2_RXDAT 70 90*4882a593Smuzhiyun #define LOCHNAGAR2_PIN_GF_AIF2_LRCLK 71 91*4882a593Smuzhiyun #define LOCHNAGAR2_PIN_GF_AIF2_TXDAT 72 92*4882a593Smuzhiyun #define LOCHNAGAR2_PIN_DSP_UART1_RX 73 93*4882a593Smuzhiyun #define LOCHNAGAR2_PIN_DSP_UART1_TX 74 94*4882a593Smuzhiyun #define LOCHNAGAR2_PIN_DSP_UART2_RX 75 95*4882a593Smuzhiyun #define LOCHNAGAR2_PIN_DSP_UART2_TX 76 96*4882a593Smuzhiyun #define LOCHNAGAR2_PIN_GF_UART2_RX 77 97*4882a593Smuzhiyun #define LOCHNAGAR2_PIN_GF_UART2_TX 78 98*4882a593Smuzhiyun #define LOCHNAGAR2_PIN_USB_UART_RX 79 99*4882a593Smuzhiyun #define LOCHNAGAR2_PIN_CDC_PDMCLK1 80 100*4882a593Smuzhiyun #define LOCHNAGAR2_PIN_CDC_PDMDAT1 81 101*4882a593Smuzhiyun #define LOCHNAGAR2_PIN_CDC_PDMCLK2 82 102*4882a593Smuzhiyun #define LOCHNAGAR2_PIN_CDC_PDMDAT2 83 103*4882a593Smuzhiyun #define LOCHNAGAR2_PIN_CDC_DMICCLK1 84 104*4882a593Smuzhiyun #define LOCHNAGAR2_PIN_CDC_DMICDAT1 85 105*4882a593Smuzhiyun #define LOCHNAGAR2_PIN_CDC_DMICCLK2 86 106*4882a593Smuzhiyun #define LOCHNAGAR2_PIN_CDC_DMICDAT2 87 107*4882a593Smuzhiyun #define LOCHNAGAR2_PIN_CDC_DMICCLK3 88 108*4882a593Smuzhiyun #define LOCHNAGAR2_PIN_CDC_DMICDAT3 89 109*4882a593Smuzhiyun #define LOCHNAGAR2_PIN_CDC_DMICCLK4 90 110*4882a593Smuzhiyun #define LOCHNAGAR2_PIN_CDC_DMICDAT4 91 111*4882a593Smuzhiyun #define LOCHNAGAR2_PIN_DSP_DMICCLK1 92 112*4882a593Smuzhiyun #define LOCHNAGAR2_PIN_DSP_DMICDAT1 93 113*4882a593Smuzhiyun #define LOCHNAGAR2_PIN_DSP_DMICCLK2 94 114*4882a593Smuzhiyun #define LOCHNAGAR2_PIN_DSP_DMICDAT2 95 115*4882a593Smuzhiyun #define LOCHNAGAR2_PIN_I2C2_SCL 96 116*4882a593Smuzhiyun #define LOCHNAGAR2_PIN_I2C2_SDA 97 117*4882a593Smuzhiyun #define LOCHNAGAR2_PIN_I2C3_SCL 98 118*4882a593Smuzhiyun #define LOCHNAGAR2_PIN_I2C3_SDA 99 119*4882a593Smuzhiyun #define LOCHNAGAR2_PIN_I2C4_SCL 100 120*4882a593Smuzhiyun #define LOCHNAGAR2_PIN_I2C4_SDA 101 121*4882a593Smuzhiyun #define LOCHNAGAR2_PIN_DSP_STANDBY 102 122*4882a593Smuzhiyun #define LOCHNAGAR2_PIN_CDC_MCLK1 103 123*4882a593Smuzhiyun #define LOCHNAGAR2_PIN_CDC_MCLK2 104 124*4882a593Smuzhiyun #define LOCHNAGAR2_PIN_DSP_CLKIN 105 125*4882a593Smuzhiyun #define LOCHNAGAR2_PIN_PSIA1_MCLK 106 126*4882a593Smuzhiyun #define LOCHNAGAR2_PIN_PSIA2_MCLK 107 127*4882a593Smuzhiyun #define LOCHNAGAR2_PIN_GF_GPIO1 108 128*4882a593Smuzhiyun #define LOCHNAGAR2_PIN_GF_GPIO5 109 129*4882a593Smuzhiyun #define LOCHNAGAR2_PIN_DSP_GPIO20 110 130*4882a593Smuzhiyun #define LOCHNAGAR2_PIN_NUM_GPIOS 111 131*4882a593Smuzhiyun 132*4882a593Smuzhiyun #endif 133