1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * This header provides constants for hisilicon pinctrl bindings. 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Copyright (c) 2015 Hisilicon Limited. 5*4882a593Smuzhiyun * Copyright (c) 2015 Linaro Limited. 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * This program is free software; you can redistribute it and/or modify 8*4882a593Smuzhiyun * it under the terms of the GNU General Public License version 2 as 9*4882a593Smuzhiyun * published by the Free Software Foundation. 10*4882a593Smuzhiyun * 11*4882a593Smuzhiyun * This program is distributed "as is" WITHOUT ANY WARRANTY of any 12*4882a593Smuzhiyun * kind, whether express or implied; without even the implied warranty 13*4882a593Smuzhiyun * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14*4882a593Smuzhiyun * GNU General Public License for more details. 15*4882a593Smuzhiyun */ 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun #ifndef _DT_BINDINGS_PINCTRL_HISI_H 18*4882a593Smuzhiyun #define _DT_BINDINGS_PINCTRL_HISI_H 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun /* iomg bit definition */ 21*4882a593Smuzhiyun #define MUX_M0 0 22*4882a593Smuzhiyun #define MUX_M1 1 23*4882a593Smuzhiyun #define MUX_M2 2 24*4882a593Smuzhiyun #define MUX_M3 3 25*4882a593Smuzhiyun #define MUX_M4 4 26*4882a593Smuzhiyun #define MUX_M5 5 27*4882a593Smuzhiyun #define MUX_M6 6 28*4882a593Smuzhiyun #define MUX_M7 7 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun /* iocg bit definition */ 31*4882a593Smuzhiyun #define PULL_MASK (3) 32*4882a593Smuzhiyun #define PULL_DIS (0) 33*4882a593Smuzhiyun #define PULL_UP (1 << 0) 34*4882a593Smuzhiyun #define PULL_DOWN (1 << 1) 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun /* drive strength definition */ 37*4882a593Smuzhiyun #define DRIVE_MASK (7 << 4) 38*4882a593Smuzhiyun #define DRIVE1_02MA (0 << 4) 39*4882a593Smuzhiyun #define DRIVE1_04MA (1 << 4) 40*4882a593Smuzhiyun #define DRIVE1_08MA (2 << 4) 41*4882a593Smuzhiyun #define DRIVE1_10MA (3 << 4) 42*4882a593Smuzhiyun #define DRIVE2_02MA (0 << 4) 43*4882a593Smuzhiyun #define DRIVE2_04MA (1 << 4) 44*4882a593Smuzhiyun #define DRIVE2_08MA (2 << 4) 45*4882a593Smuzhiyun #define DRIVE2_10MA (3 << 4) 46*4882a593Smuzhiyun #define DRIVE3_04MA (0 << 4) 47*4882a593Smuzhiyun #define DRIVE3_08MA (1 << 4) 48*4882a593Smuzhiyun #define DRIVE3_12MA (2 << 4) 49*4882a593Smuzhiyun #define DRIVE3_16MA (3 << 4) 50*4882a593Smuzhiyun #define DRIVE3_20MA (4 << 4) 51*4882a593Smuzhiyun #define DRIVE3_24MA (5 << 4) 52*4882a593Smuzhiyun #define DRIVE3_32MA (6 << 4) 53*4882a593Smuzhiyun #define DRIVE3_40MA (7 << 4) 54*4882a593Smuzhiyun #define DRIVE4_02MA (0 << 4) 55*4882a593Smuzhiyun #define DRIVE4_04MA (2 << 4) 56*4882a593Smuzhiyun #define DRIVE4_08MA (4 << 4) 57*4882a593Smuzhiyun #define DRIVE4_10MA (6 << 4) 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun /* drive strength definition for hi3660 */ 60*4882a593Smuzhiyun #define DRIVE6_MASK (15 << 4) 61*4882a593Smuzhiyun #define DRIVE6_04MA (0 << 4) 62*4882a593Smuzhiyun #define DRIVE6_12MA (4 << 4) 63*4882a593Smuzhiyun #define DRIVE6_19MA (8 << 4) 64*4882a593Smuzhiyun #define DRIVE6_27MA (10 << 4) 65*4882a593Smuzhiyun #define DRIVE6_32MA (15 << 4) 66*4882a593Smuzhiyun #define DRIVE7_02MA (0 << 4) 67*4882a593Smuzhiyun #define DRIVE7_04MA (1 << 4) 68*4882a593Smuzhiyun #define DRIVE7_06MA (2 << 4) 69*4882a593Smuzhiyun #define DRIVE7_08MA (3 << 4) 70*4882a593Smuzhiyun #define DRIVE7_10MA (4 << 4) 71*4882a593Smuzhiyun #define DRIVE7_12MA (5 << 4) 72*4882a593Smuzhiyun #define DRIVE7_14MA (6 << 4) 73*4882a593Smuzhiyun #define DRIVE7_16MA (7 << 4) 74*4882a593Smuzhiyun #endif 75