1*4882a593Smuzhiyun /* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (c) 2021 Rockchip Electronics Co., Ltd. 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun #ifndef _DT_BINDINGS_PHY_SNPS_PCIE3 7*4882a593Smuzhiyun #define _DT_BINDINGS_PHY_SNPS_PCIE3 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun /* 10*4882a593Smuzhiyun * pcie30_phy_mode[2:0] 11*4882a593Smuzhiyun * bit2: aggregation 12*4882a593Smuzhiyun * bit1: bifurcation for port 1 13*4882a593Smuzhiyun * bit0: bifurcation for port 0 14*4882a593Smuzhiyun */ 15*4882a593Smuzhiyun #define PHY_MODE_PCIE_AGGREGATION 4 /* PCIe3x4 */ 16*4882a593Smuzhiyun #define PHY_MODE_PCIE_NANBNB 0 /* P1:PCIe3x2 + P0:PCIe3x2 */ 17*4882a593Smuzhiyun #define PHY_MODE_PCIE_NANBBI 1 /* P1:PCIe3x2 + P0:PCIe3x1*2 */ 18*4882a593Smuzhiyun #define PHY_MODE_PCIE_NABINB 2 /* P1:PCIe3x1*2 + P0:PCIe3x2 */ 19*4882a593Smuzhiyun #define PHY_MODE_PCIE_NABIBI 3 /* P1:PCIe3x1*2 + P0:PCIe3x1*2 */ 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun #endif /* _DT_BINDINGS_PHY_SNPS_PCIE3 */ 22