1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * This header provides constants for SERDES MUX for TI SoCs 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun #ifndef _DT_BINDINGS_MUX_TI_SERDES 7*4882a593Smuzhiyun #define _DT_BINDINGS_MUX_TI_SERDES 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun /* J721E */ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #define J721E_SERDES0_LANE0_QSGMII_LANE1 0x0 12*4882a593Smuzhiyun #define J721E_SERDES0_LANE0_PCIE0_LANE0 0x1 13*4882a593Smuzhiyun #define J721E_SERDES0_LANE0_USB3_0_SWAP 0x2 14*4882a593Smuzhiyun #define J721E_SERDES0_LANE0_IP4_UNUSED 0x3 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun #define J721E_SERDES0_LANE1_QSGMII_LANE2 0x0 17*4882a593Smuzhiyun #define J721E_SERDES0_LANE1_PCIE0_LANE1 0x1 18*4882a593Smuzhiyun #define J721E_SERDES0_LANE1_USB3_0 0x2 19*4882a593Smuzhiyun #define J721E_SERDES0_LANE1_IP4_UNUSED 0x3 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun #define J721E_SERDES1_LANE0_QSGMII_LANE3 0x0 22*4882a593Smuzhiyun #define J721E_SERDES1_LANE0_PCIE1_LANE0 0x1 23*4882a593Smuzhiyun #define J721E_SERDES1_LANE0_USB3_1_SWAP 0x2 24*4882a593Smuzhiyun #define J721E_SERDES1_LANE0_SGMII_LANE0 0x3 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun #define J721E_SERDES1_LANE1_QSGMII_LANE4 0x0 27*4882a593Smuzhiyun #define J721E_SERDES1_LANE1_PCIE1_LANE1 0x1 28*4882a593Smuzhiyun #define J721E_SERDES1_LANE1_USB3_1 0x2 29*4882a593Smuzhiyun #define J721E_SERDES1_LANE1_SGMII_LANE1 0x3 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun #define J721E_SERDES2_LANE0_IP1_UNUSED 0x0 32*4882a593Smuzhiyun #define J721E_SERDES2_LANE0_PCIE2_LANE0 0x1 33*4882a593Smuzhiyun #define J721E_SERDES2_LANE0_USB3_1_SWAP 0x2 34*4882a593Smuzhiyun #define J721E_SERDES2_LANE0_SGMII_LANE0 0x3 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun #define J721E_SERDES2_LANE1_IP1_UNUSED 0x0 37*4882a593Smuzhiyun #define J721E_SERDES2_LANE1_PCIE2_LANE1 0x1 38*4882a593Smuzhiyun #define J721E_SERDES2_LANE1_USB3_1 0x2 39*4882a593Smuzhiyun #define J721E_SERDES2_LANE1_SGMII_LANE1 0x3 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun #define J721E_SERDES3_LANE0_IP1_UNUSED 0x0 42*4882a593Smuzhiyun #define J721E_SERDES3_LANE0_PCIE3_LANE0 0x1 43*4882a593Smuzhiyun #define J721E_SERDES3_LANE0_USB3_0_SWAP 0x2 44*4882a593Smuzhiyun #define J721E_SERDES3_LANE0_IP4_UNUSED 0x3 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun #define J721E_SERDES3_LANE1_IP1_UNUSED 0x0 47*4882a593Smuzhiyun #define J721E_SERDES3_LANE1_PCIE3_LANE1 0x1 48*4882a593Smuzhiyun #define J721E_SERDES3_LANE1_USB3_0 0x2 49*4882a593Smuzhiyun #define J721E_SERDES3_LANE1_IP4_UNUSED 0x3 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun #define J721E_SERDES4_LANE0_EDP_LANE0 0x0 52*4882a593Smuzhiyun #define J721E_SERDES4_LANE0_IP2_UNUSED 0x1 53*4882a593Smuzhiyun #define J721E_SERDES4_LANE0_QSGMII_LANE5 0x2 54*4882a593Smuzhiyun #define J721E_SERDES4_LANE0_IP4_UNUSED 0x3 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun #define J721E_SERDES4_LANE1_EDP_LANE1 0x0 57*4882a593Smuzhiyun #define J721E_SERDES4_LANE1_IP2_UNUSED 0x1 58*4882a593Smuzhiyun #define J721E_SERDES4_LANE1_QSGMII_LANE6 0x2 59*4882a593Smuzhiyun #define J721E_SERDES4_LANE1_IP4_UNUSED 0x3 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun #define J721E_SERDES4_LANE2_EDP_LANE2 0x0 62*4882a593Smuzhiyun #define J721E_SERDES4_LANE2_IP2_UNUSED 0x1 63*4882a593Smuzhiyun #define J721E_SERDES4_LANE2_QSGMII_LANE7 0x2 64*4882a593Smuzhiyun #define J721E_SERDES4_LANE2_IP4_UNUSED 0x3 65*4882a593Smuzhiyun 66*4882a593Smuzhiyun #define J721E_SERDES4_LANE3_EDP_LANE3 0x0 67*4882a593Smuzhiyun #define J721E_SERDES4_LANE3_IP2_UNUSED 0x1 68*4882a593Smuzhiyun #define J721E_SERDES4_LANE3_QSGMII_LANE8 0x2 69*4882a593Smuzhiyun #define J721E_SERDES4_LANE3_IP4_UNUSED 0x3 70*4882a593Smuzhiyun 71*4882a593Smuzhiyun /* J7200 */ 72*4882a593Smuzhiyun 73*4882a593Smuzhiyun #define J7200_SERDES0_LANE0_QSGMII_LANE3 0x0 74*4882a593Smuzhiyun #define J7200_SERDES0_LANE0_PCIE1_LANE0 0x1 75*4882a593Smuzhiyun #define J7200_SERDES0_LANE0_IP3_UNUSED 0x2 76*4882a593Smuzhiyun #define J7200_SERDES0_LANE0_IP4_UNUSED 0x3 77*4882a593Smuzhiyun 78*4882a593Smuzhiyun #define J7200_SERDES0_LANE1_QSGMII_LANE4 0x0 79*4882a593Smuzhiyun #define J7200_SERDES0_LANE1_PCIE1_LANE1 0x1 80*4882a593Smuzhiyun #define J7200_SERDES0_LANE1_IP3_UNUSED 0x2 81*4882a593Smuzhiyun #define J7200_SERDES0_LANE1_IP4_UNUSED 0x3 82*4882a593Smuzhiyun 83*4882a593Smuzhiyun #define J7200_SERDES0_LANE2_QSGMII_LANE1 0x0 84*4882a593Smuzhiyun #define J7200_SERDES0_LANE2_PCIE1_LANE2 0x1 85*4882a593Smuzhiyun #define J7200_SERDES0_LANE2_IP3_UNUSED 0x2 86*4882a593Smuzhiyun #define J7200_SERDES0_LANE2_IP4_UNUSED 0x3 87*4882a593Smuzhiyun 88*4882a593Smuzhiyun #define J7200_SERDES0_LANE3_QSGMII_LANE2 0x0 89*4882a593Smuzhiyun #define J7200_SERDES0_LANE3_PCIE1_LANE3 0x1 90*4882a593Smuzhiyun #define J7200_SERDES0_LANE3_USB 0x2 91*4882a593Smuzhiyun #define J7200_SERDES0_LANE3_IP4_UNUSED 0x3 92*4882a593Smuzhiyun 93*4882a593Smuzhiyun #endif /* _DT_BINDINGS_MUX_TI_SERDES */ 94