1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * This header provides constants for the STM32H7 RCC IP 3*4882a593Smuzhiyun */ 4*4882a593Smuzhiyun 5*4882a593Smuzhiyun #ifndef _DT_BINDINGS_MFD_STM32H7_RCC_H 6*4882a593Smuzhiyun #define _DT_BINDINGS_MFD_STM32H7_RCC_H 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun /* AHB3 */ 9*4882a593Smuzhiyun #define STM32H7_RCC_AHB3_MDMA 0 10*4882a593Smuzhiyun #define STM32H7_RCC_AHB3_DMA2D 4 11*4882a593Smuzhiyun #define STM32H7_RCC_AHB3_JPGDEC 5 12*4882a593Smuzhiyun #define STM32H7_RCC_AHB3_FMC 12 13*4882a593Smuzhiyun #define STM32H7_RCC_AHB3_QUADSPI 14 14*4882a593Smuzhiyun #define STM32H7_RCC_AHB3_SDMMC1 16 15*4882a593Smuzhiyun #define STM32H7_RCC_AHB3_CPU 31 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun #define STM32H7_AHB3_RESET(bit) (STM32H7_RCC_AHB3_##bit + (0x7C * 8)) 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun /* AHB1 */ 20*4882a593Smuzhiyun #define STM32H7_RCC_AHB1_DMA1 0 21*4882a593Smuzhiyun #define STM32H7_RCC_AHB1_DMA2 1 22*4882a593Smuzhiyun #define STM32H7_RCC_AHB1_ADC12 5 23*4882a593Smuzhiyun #define STM32H7_RCC_AHB1_ART 14 24*4882a593Smuzhiyun #define STM32H7_RCC_AHB1_ETH1MAC 15 25*4882a593Smuzhiyun #define STM32H7_RCC_AHB1_USB1OTG 25 26*4882a593Smuzhiyun #define STM32H7_RCC_AHB1_USB2OTG 27 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun #define STM32H7_AHB1_RESET(bit) (STM32H7_RCC_AHB1_##bit + (0x80 * 8)) 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun /* AHB2 */ 31*4882a593Smuzhiyun #define STM32H7_RCC_AHB2_CAMITF 0 32*4882a593Smuzhiyun #define STM32H7_RCC_AHB2_CRYPT 4 33*4882a593Smuzhiyun #define STM32H7_RCC_AHB2_HASH 5 34*4882a593Smuzhiyun #define STM32H7_RCC_AHB2_RNG 6 35*4882a593Smuzhiyun #define STM32H7_RCC_AHB2_SDMMC2 9 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun #define STM32H7_AHB2_RESET(bit) (STM32H7_RCC_AHB2_##bit + (0x84 * 8)) 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun /* AHB4 */ 40*4882a593Smuzhiyun #define STM32H7_RCC_AHB4_GPIOA 0 41*4882a593Smuzhiyun #define STM32H7_RCC_AHB4_GPIOB 1 42*4882a593Smuzhiyun #define STM32H7_RCC_AHB4_GPIOC 2 43*4882a593Smuzhiyun #define STM32H7_RCC_AHB4_GPIOD 3 44*4882a593Smuzhiyun #define STM32H7_RCC_AHB4_GPIOE 4 45*4882a593Smuzhiyun #define STM32H7_RCC_AHB4_GPIOF 5 46*4882a593Smuzhiyun #define STM32H7_RCC_AHB4_GPIOG 6 47*4882a593Smuzhiyun #define STM32H7_RCC_AHB4_GPIOH 7 48*4882a593Smuzhiyun #define STM32H7_RCC_AHB4_GPIOI 8 49*4882a593Smuzhiyun #define STM32H7_RCC_AHB4_GPIOJ 9 50*4882a593Smuzhiyun #define STM32H7_RCC_AHB4_GPIOK 10 51*4882a593Smuzhiyun #define STM32H7_RCC_AHB4_CRC 19 52*4882a593Smuzhiyun #define STM32H7_RCC_AHB4_BDMA 21 53*4882a593Smuzhiyun #define STM32H7_RCC_AHB4_ADC3 24 54*4882a593Smuzhiyun #define STM32H7_RCC_AHB4_HSEM 25 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun #define STM32H7_AHB4_RESET(bit) (STM32H7_RCC_AHB4_##bit + (0x88 * 8)) 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun /* APB3 */ 59*4882a593Smuzhiyun #define STM32H7_RCC_APB3_LTDC 3 60*4882a593Smuzhiyun #define STM32H7_RCC_APB3_DSI 4 61*4882a593Smuzhiyun 62*4882a593Smuzhiyun #define STM32H7_APB3_RESET(bit) (STM32H7_RCC_APB3_##bit + (0x8C * 8)) 63*4882a593Smuzhiyun 64*4882a593Smuzhiyun /* APB1L */ 65*4882a593Smuzhiyun #define STM32H7_RCC_APB1L_TIM2 0 66*4882a593Smuzhiyun #define STM32H7_RCC_APB1L_TIM3 1 67*4882a593Smuzhiyun #define STM32H7_RCC_APB1L_TIM4 2 68*4882a593Smuzhiyun #define STM32H7_RCC_APB1L_TIM5 3 69*4882a593Smuzhiyun #define STM32H7_RCC_APB1L_TIM6 4 70*4882a593Smuzhiyun #define STM32H7_RCC_APB1L_TIM7 5 71*4882a593Smuzhiyun #define STM32H7_RCC_APB1L_TIM12 6 72*4882a593Smuzhiyun #define STM32H7_RCC_APB1L_TIM13 7 73*4882a593Smuzhiyun #define STM32H7_RCC_APB1L_TIM14 8 74*4882a593Smuzhiyun #define STM32H7_RCC_APB1L_LPTIM1 9 75*4882a593Smuzhiyun #define STM32H7_RCC_APB1L_SPI2 14 76*4882a593Smuzhiyun #define STM32H7_RCC_APB1L_SPI3 15 77*4882a593Smuzhiyun #define STM32H7_RCC_APB1L_SPDIF_RX 16 78*4882a593Smuzhiyun #define STM32H7_RCC_APB1L_USART2 17 79*4882a593Smuzhiyun #define STM32H7_RCC_APB1L_USART3 18 80*4882a593Smuzhiyun #define STM32H7_RCC_APB1L_UART4 19 81*4882a593Smuzhiyun #define STM32H7_RCC_APB1L_UART5 20 82*4882a593Smuzhiyun #define STM32H7_RCC_APB1L_I2C1 21 83*4882a593Smuzhiyun #define STM32H7_RCC_APB1L_I2C2 22 84*4882a593Smuzhiyun #define STM32H7_RCC_APB1L_I2C3 23 85*4882a593Smuzhiyun #define STM32H7_RCC_APB1L_HDMICEC 27 86*4882a593Smuzhiyun #define STM32H7_RCC_APB1L_DAC12 29 87*4882a593Smuzhiyun #define STM32H7_RCC_APB1L_USART7 30 88*4882a593Smuzhiyun #define STM32H7_RCC_APB1L_USART8 31 89*4882a593Smuzhiyun 90*4882a593Smuzhiyun #define STM32H7_APB1L_RESET(bit) (STM32H7_RCC_APB1L_##bit + (0x90 * 8)) 91*4882a593Smuzhiyun 92*4882a593Smuzhiyun /* APB1H */ 93*4882a593Smuzhiyun #define STM32H7_RCC_APB1H_CRS 1 94*4882a593Smuzhiyun #define STM32H7_RCC_APB1H_SWP 2 95*4882a593Smuzhiyun #define STM32H7_RCC_APB1H_OPAMP 4 96*4882a593Smuzhiyun #define STM32H7_RCC_APB1H_MDIOS 5 97*4882a593Smuzhiyun #define STM32H7_RCC_APB1H_FDCAN 8 98*4882a593Smuzhiyun 99*4882a593Smuzhiyun #define STM32H7_APB1H_RESET(bit) (STM32H7_RCC_APB1H_##bit + (0x94 * 8)) 100*4882a593Smuzhiyun 101*4882a593Smuzhiyun /* APB2 */ 102*4882a593Smuzhiyun #define STM32H7_RCC_APB2_TIM1 0 103*4882a593Smuzhiyun #define STM32H7_RCC_APB2_TIM8 1 104*4882a593Smuzhiyun #define STM32H7_RCC_APB2_USART1 4 105*4882a593Smuzhiyun #define STM32H7_RCC_APB2_USART6 5 106*4882a593Smuzhiyun #define STM32H7_RCC_APB2_SPI1 12 107*4882a593Smuzhiyun #define STM32H7_RCC_APB2_SPI4 13 108*4882a593Smuzhiyun #define STM32H7_RCC_APB2_TIM15 16 109*4882a593Smuzhiyun #define STM32H7_RCC_APB2_TIM16 17 110*4882a593Smuzhiyun #define STM32H7_RCC_APB2_TIM17 18 111*4882a593Smuzhiyun #define STM32H7_RCC_APB2_SPI5 20 112*4882a593Smuzhiyun #define STM32H7_RCC_APB2_SAI1 22 113*4882a593Smuzhiyun #define STM32H7_RCC_APB2_SAI2 23 114*4882a593Smuzhiyun #define STM32H7_RCC_APB2_SAI3 24 115*4882a593Smuzhiyun #define STM32H7_RCC_APB2_DFSDM1 28 116*4882a593Smuzhiyun #define STM32H7_RCC_APB2_HRTIM 29 117*4882a593Smuzhiyun 118*4882a593Smuzhiyun #define STM32H7_APB2_RESET(bit) (STM32H7_RCC_APB2_##bit + (0x98 * 8)) 119*4882a593Smuzhiyun 120*4882a593Smuzhiyun /* APB4 */ 121*4882a593Smuzhiyun #define STM32H7_RCC_APB4_SYSCFG 1 122*4882a593Smuzhiyun #define STM32H7_RCC_APB4_LPUART1 3 123*4882a593Smuzhiyun #define STM32H7_RCC_APB4_SPI6 5 124*4882a593Smuzhiyun #define STM32H7_RCC_APB4_I2C4 7 125*4882a593Smuzhiyun #define STM32H7_RCC_APB4_LPTIM2 9 126*4882a593Smuzhiyun #define STM32H7_RCC_APB4_LPTIM3 10 127*4882a593Smuzhiyun #define STM32H7_RCC_APB4_LPTIM4 11 128*4882a593Smuzhiyun #define STM32H7_RCC_APB4_LPTIM5 12 129*4882a593Smuzhiyun #define STM32H7_RCC_APB4_COMP12 14 130*4882a593Smuzhiyun #define STM32H7_RCC_APB4_VREF 15 131*4882a593Smuzhiyun #define STM32H7_RCC_APB4_SAI4 21 132*4882a593Smuzhiyun #define STM32H7_RCC_APB4_TMPSENS 26 133*4882a593Smuzhiyun 134*4882a593Smuzhiyun #define STM32H7_APB4_RESET(bit) (STM32H7_RCC_APB4_##bit + (0x9C * 8)) 135*4882a593Smuzhiyun 136*4882a593Smuzhiyun #endif /* _DT_BINDINGS_MFD_STM32H7_RCC_H */ 137