1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * This header provides constants for the STM32F7 RCC IP 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun #ifndef _DT_BINDINGS_MFD_STM32F7_RCC_H 7*4882a593Smuzhiyun #define _DT_BINDINGS_MFD_STM32F7_RCC_H 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun /* AHB1 */ 10*4882a593Smuzhiyun #define STM32F7_RCC_AHB1_GPIOA 0 11*4882a593Smuzhiyun #define STM32F7_RCC_AHB1_GPIOB 1 12*4882a593Smuzhiyun #define STM32F7_RCC_AHB1_GPIOC 2 13*4882a593Smuzhiyun #define STM32F7_RCC_AHB1_GPIOD 3 14*4882a593Smuzhiyun #define STM32F7_RCC_AHB1_GPIOE 4 15*4882a593Smuzhiyun #define STM32F7_RCC_AHB1_GPIOF 5 16*4882a593Smuzhiyun #define STM32F7_RCC_AHB1_GPIOG 6 17*4882a593Smuzhiyun #define STM32F7_RCC_AHB1_GPIOH 7 18*4882a593Smuzhiyun #define STM32F7_RCC_AHB1_GPIOI 8 19*4882a593Smuzhiyun #define STM32F7_RCC_AHB1_GPIOJ 9 20*4882a593Smuzhiyun #define STM32F7_RCC_AHB1_GPIOK 10 21*4882a593Smuzhiyun #define STM32F7_RCC_AHB1_CRC 12 22*4882a593Smuzhiyun #define STM32F7_RCC_AHB1_BKPSRAM 18 23*4882a593Smuzhiyun #define STM32F7_RCC_AHB1_DTCMRAM 20 24*4882a593Smuzhiyun #define STM32F7_RCC_AHB1_DMA1 21 25*4882a593Smuzhiyun #define STM32F7_RCC_AHB1_DMA2 22 26*4882a593Smuzhiyun #define STM32F7_RCC_AHB1_DMA2D 23 27*4882a593Smuzhiyun #define STM32F7_RCC_AHB1_ETHMAC 25 28*4882a593Smuzhiyun #define STM32F7_RCC_AHB1_ETHMACTX 26 29*4882a593Smuzhiyun #define STM32F7_RCC_AHB1_ETHMACRX 27 30*4882a593Smuzhiyun #define STM32FF_RCC_AHB1_ETHMACPTP 28 31*4882a593Smuzhiyun #define STM32F7_RCC_AHB1_OTGHS 29 32*4882a593Smuzhiyun #define STM32F7_RCC_AHB1_OTGHSULPI 30 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun #define STM32F7_AHB1_RESET(bit) (STM32F7_RCC_AHB1_##bit + (0x10 * 8)) 35*4882a593Smuzhiyun #define STM32F7_AHB1_CLOCK(bit) (STM32F7_RCC_AHB1_##bit) 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun /* AHB2 */ 39*4882a593Smuzhiyun #define STM32F7_RCC_AHB2_DCMI 0 40*4882a593Smuzhiyun #define STM32F7_RCC_AHB2_CRYP 4 41*4882a593Smuzhiyun #define STM32F7_RCC_AHB2_HASH 5 42*4882a593Smuzhiyun #define STM32F7_RCC_AHB2_RNG 6 43*4882a593Smuzhiyun #define STM32F7_RCC_AHB2_OTGFS 7 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun #define STM32F7_AHB2_RESET(bit) (STM32F7_RCC_AHB2_##bit + (0x14 * 8)) 46*4882a593Smuzhiyun #define STM32F7_AHB2_CLOCK(bit) (STM32F7_RCC_AHB2_##bit + 0x20) 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun /* AHB3 */ 49*4882a593Smuzhiyun #define STM32F7_RCC_AHB3_FMC 0 50*4882a593Smuzhiyun #define STM32F7_RCC_AHB3_QSPI 1 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun #define STM32F7_AHB3_RESET(bit) (STM32F7_RCC_AHB3_##bit + (0x18 * 8)) 53*4882a593Smuzhiyun #define STM32F7_AHB3_CLOCK(bit) (STM32F7_RCC_AHB3_##bit + 0x40) 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun /* APB1 */ 56*4882a593Smuzhiyun #define STM32F7_RCC_APB1_TIM2 0 57*4882a593Smuzhiyun #define STM32F7_RCC_APB1_TIM3 1 58*4882a593Smuzhiyun #define STM32F7_RCC_APB1_TIM4 2 59*4882a593Smuzhiyun #define STM32F7_RCC_APB1_TIM5 3 60*4882a593Smuzhiyun #define STM32F7_RCC_APB1_TIM6 4 61*4882a593Smuzhiyun #define STM32F7_RCC_APB1_TIM7 5 62*4882a593Smuzhiyun #define STM32F7_RCC_APB1_TIM12 6 63*4882a593Smuzhiyun #define STM32F7_RCC_APB1_TIM13 7 64*4882a593Smuzhiyun #define STM32F7_RCC_APB1_TIM14 8 65*4882a593Smuzhiyun #define STM32F7_RCC_APB1_LPTIM1 9 66*4882a593Smuzhiyun #define STM32F7_RCC_APB1_WWDG 11 67*4882a593Smuzhiyun #define STM32F7_RCC_APB1_SPI2 14 68*4882a593Smuzhiyun #define STM32F7_RCC_APB1_SPI3 15 69*4882a593Smuzhiyun #define STM32F7_RCC_APB1_SPDIFRX 16 70*4882a593Smuzhiyun #define STM32F7_RCC_APB1_UART2 17 71*4882a593Smuzhiyun #define STM32F7_RCC_APB1_UART3 18 72*4882a593Smuzhiyun #define STM32F7_RCC_APB1_UART4 19 73*4882a593Smuzhiyun #define STM32F7_RCC_APB1_UART5 20 74*4882a593Smuzhiyun #define STM32F7_RCC_APB1_I2C1 21 75*4882a593Smuzhiyun #define STM32F7_RCC_APB1_I2C2 22 76*4882a593Smuzhiyun #define STM32F7_RCC_APB1_I2C3 23 77*4882a593Smuzhiyun #define STM32F7_RCC_APB1_I2C4 24 78*4882a593Smuzhiyun #define STM32F7_RCC_APB1_CAN1 25 79*4882a593Smuzhiyun #define STM32F7_RCC_APB1_CAN2 26 80*4882a593Smuzhiyun #define STM32F7_RCC_APB1_CEC 27 81*4882a593Smuzhiyun #define STM32F7_RCC_APB1_PWR 28 82*4882a593Smuzhiyun #define STM32F7_RCC_APB1_DAC 29 83*4882a593Smuzhiyun #define STM32F7_RCC_APB1_UART7 30 84*4882a593Smuzhiyun #define STM32F7_RCC_APB1_UART8 31 85*4882a593Smuzhiyun 86*4882a593Smuzhiyun #define STM32F7_APB1_RESET(bit) (STM32F7_RCC_APB1_##bit + (0x20 * 8)) 87*4882a593Smuzhiyun #define STM32F7_APB1_CLOCK(bit) (STM32F7_RCC_APB1_##bit + 0x80) 88*4882a593Smuzhiyun 89*4882a593Smuzhiyun /* APB2 */ 90*4882a593Smuzhiyun #define STM32F7_RCC_APB2_TIM1 0 91*4882a593Smuzhiyun #define STM32F7_RCC_APB2_TIM8 1 92*4882a593Smuzhiyun #define STM32F7_RCC_APB2_USART1 4 93*4882a593Smuzhiyun #define STM32F7_RCC_APB2_USART6 5 94*4882a593Smuzhiyun #define STM32F7_RCC_APB2_SDMMC2 7 95*4882a593Smuzhiyun #define STM32F7_RCC_APB2_ADC1 8 96*4882a593Smuzhiyun #define STM32F7_RCC_APB2_ADC2 9 97*4882a593Smuzhiyun #define STM32F7_RCC_APB2_ADC3 10 98*4882a593Smuzhiyun #define STM32F7_RCC_APB2_SDMMC1 11 99*4882a593Smuzhiyun #define STM32F7_RCC_APB2_SPI1 12 100*4882a593Smuzhiyun #define STM32F7_RCC_APB2_SPI4 13 101*4882a593Smuzhiyun #define STM32F7_RCC_APB2_SYSCFG 14 102*4882a593Smuzhiyun #define STM32F7_RCC_APB2_TIM9 16 103*4882a593Smuzhiyun #define STM32F7_RCC_APB2_TIM10 17 104*4882a593Smuzhiyun #define STM32F7_RCC_APB2_TIM11 18 105*4882a593Smuzhiyun #define STM32F7_RCC_APB2_SPI5 20 106*4882a593Smuzhiyun #define STM32F7_RCC_APB2_SPI6 21 107*4882a593Smuzhiyun #define STM32F7_RCC_APB2_SAI1 22 108*4882a593Smuzhiyun #define STM32F7_RCC_APB2_SAI2 23 109*4882a593Smuzhiyun #define STM32F7_RCC_APB2_LTDC 26 110*4882a593Smuzhiyun 111*4882a593Smuzhiyun #define STM32F7_APB2_RESET(bit) (STM32F7_RCC_APB2_##bit + (0x24 * 8)) 112*4882a593Smuzhiyun #define STM32F7_APB2_CLOCK(bit) (STM32F7_RCC_APB2_##bit + 0xA0) 113*4882a593Smuzhiyun 114*4882a593Smuzhiyun #endif /* _DT_BINDINGS_MFD_STM32F7_RCC_H */ 115