1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * This header provides macros for MAXIM MAX77620 device bindings. 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (c) 2016, NVIDIA Corporation. 6*4882a593Smuzhiyun * Author: Laxman Dewangan <ldewangan@nvidia.com> 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #ifndef _DT_BINDINGS_MFD_MAX77620_H 10*4882a593Smuzhiyun #define _DT_BINDINGS_MFD_MAX77620_H 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun /* MAX77620 interrupts */ 13*4882a593Smuzhiyun #define MAX77620_IRQ_TOP_GLBL 0 /* Low-Battery */ 14*4882a593Smuzhiyun #define MAX77620_IRQ_TOP_SD 1 /* SD power fail */ 15*4882a593Smuzhiyun #define MAX77620_IRQ_TOP_LDO 2 /* LDO power fail */ 16*4882a593Smuzhiyun #define MAX77620_IRQ_TOP_GPIO 3 /* GPIO internal int to MAX77620 */ 17*4882a593Smuzhiyun #define MAX77620_IRQ_TOP_RTC 4 /* RTC */ 18*4882a593Smuzhiyun #define MAX77620_IRQ_TOP_32K 5 /* 32kHz oscillator */ 19*4882a593Smuzhiyun #define MAX77620_IRQ_TOP_ONOFF 6 /* ON/OFF oscillator */ 20*4882a593Smuzhiyun #define MAX77620_IRQ_LBT_MBATLOW 7 /* Thermal alarm status, > 120C */ 21*4882a593Smuzhiyun #define MAX77620_IRQ_LBT_TJALRM1 8 /* Thermal alarm status, > 120C */ 22*4882a593Smuzhiyun #define MAX77620_IRQ_LBT_TJALRM2 9 /* Thermal alarm status, > 140C */ 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun /* FPS event source */ 25*4882a593Smuzhiyun #define MAX77620_FPS_EVENT_SRC_EN0 0 26*4882a593Smuzhiyun #define MAX77620_FPS_EVENT_SRC_EN1 1 27*4882a593Smuzhiyun #define MAX77620_FPS_EVENT_SRC_SW 2 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun /* Device state when FPS event LOW */ 30*4882a593Smuzhiyun #define MAX77620_FPS_INACTIVE_STATE_SLEEP 0 31*4882a593Smuzhiyun #define MAX77620_FPS_INACTIVE_STATE_LOW_POWER 1 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun /* FPS source */ 34*4882a593Smuzhiyun #define MAX77620_FPS_SRC_0 0 35*4882a593Smuzhiyun #define MAX77620_FPS_SRC_1 1 36*4882a593Smuzhiyun #define MAX77620_FPS_SRC_2 2 37*4882a593Smuzhiyun #define MAX77620_FPS_SRC_NONE 3 38*4882a593Smuzhiyun #define MAX77620_FPS_SRC_DEF 4 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun #endif 41