1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * This header provides constants for the PRCMU bindings. 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #ifndef _DT_BINDINGS_MFD_PRCMU_H 8*4882a593Smuzhiyun #define _DT_BINDINGS_MFD_PRCMU_H 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun /* 11*4882a593Smuzhiyun * Clock identifiers. 12*4882a593Smuzhiyun */ 13*4882a593Smuzhiyun #define ARMCLK 0 14*4882a593Smuzhiyun #define PRCMU_ACLK 1 15*4882a593Smuzhiyun #define PRCMU_SVAMMCSPCLK 2 16*4882a593Smuzhiyun #define PRCMU_SDMMCHCLK 2 /* DBx540 only. */ 17*4882a593Smuzhiyun #define PRCMU_SIACLK 3 18*4882a593Smuzhiyun #define PRCMU_SIAMMDSPCLK 3 /* DBx540 only. */ 19*4882a593Smuzhiyun #define PRCMU_SGACLK 4 20*4882a593Smuzhiyun #define PRCMU_UARTCLK 5 21*4882a593Smuzhiyun #define PRCMU_MSP02CLK 6 22*4882a593Smuzhiyun #define PRCMU_MSP1CLK 7 23*4882a593Smuzhiyun #define PRCMU_I2CCLK 8 24*4882a593Smuzhiyun #define PRCMU_SDMMCCLK 9 25*4882a593Smuzhiyun #define PRCMU_SLIMCLK 10 26*4882a593Smuzhiyun #define PRCMU_CAMCLK 10 /* DBx540 only. */ 27*4882a593Smuzhiyun #define PRCMU_PER1CLK 11 28*4882a593Smuzhiyun #define PRCMU_PER2CLK 12 29*4882a593Smuzhiyun #define PRCMU_PER3CLK 13 30*4882a593Smuzhiyun #define PRCMU_PER5CLK 14 31*4882a593Smuzhiyun #define PRCMU_PER6CLK 15 32*4882a593Smuzhiyun #define PRCMU_PER7CLK 16 33*4882a593Smuzhiyun #define PRCMU_LCDCLK 17 34*4882a593Smuzhiyun #define PRCMU_BMLCLK 18 35*4882a593Smuzhiyun #define PRCMU_HSITXCLK 19 36*4882a593Smuzhiyun #define PRCMU_HSIRXCLK 20 37*4882a593Smuzhiyun #define PRCMU_HDMICLK 21 38*4882a593Smuzhiyun #define PRCMU_APEATCLK 22 39*4882a593Smuzhiyun #define PRCMU_APETRACECLK 23 40*4882a593Smuzhiyun #define PRCMU_MCDECLK 24 41*4882a593Smuzhiyun #define PRCMU_IPI2CCLK 25 42*4882a593Smuzhiyun #define PRCMU_DSIALTCLK 26 43*4882a593Smuzhiyun #define PRCMU_DMACLK 27 44*4882a593Smuzhiyun #define PRCMU_B2R2CLK 28 45*4882a593Smuzhiyun #define PRCMU_TVCLK 29 46*4882a593Smuzhiyun #define SPARE_UNIPROCLK 30 47*4882a593Smuzhiyun #define PRCMU_SSPCLK 31 48*4882a593Smuzhiyun #define PRCMU_RNGCLK 32 49*4882a593Smuzhiyun #define PRCMU_UICCCLK 33 50*4882a593Smuzhiyun #define PRCMU_G1CLK 34 /* DBx540 only. */ 51*4882a593Smuzhiyun #define PRCMU_HVACLK 35 /* DBx540 only. */ 52*4882a593Smuzhiyun #define PRCMU_SPARE1CLK 36 53*4882a593Smuzhiyun #define PRCMU_SPARE2CLK 37 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun #define PRCMU_NUM_REG_CLOCKS 38 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun #define PRCMU_RTCCLK PRCMU_NUM_REG_CLOCKS 58*4882a593Smuzhiyun #define PRCMU_SYSCLK 39 59*4882a593Smuzhiyun #define PRCMU_CDCLK 40 60*4882a593Smuzhiyun #define PRCMU_TIMCLK 41 61*4882a593Smuzhiyun #define PRCMU_PLLSOC0 42 62*4882a593Smuzhiyun #define PRCMU_PLLSOC1 43 63*4882a593Smuzhiyun #define PRCMU_ARMSS 44 64*4882a593Smuzhiyun #define PRCMU_PLLDDR 45 65*4882a593Smuzhiyun 66*4882a593Smuzhiyun /* DSI Clocks */ 67*4882a593Smuzhiyun #define PRCMU_PLLDSI 46 68*4882a593Smuzhiyun #define PRCMU_DSI0CLK 47 69*4882a593Smuzhiyun #define PRCMU_DSI1CLK 48 70*4882a593Smuzhiyun #define PRCMU_DSI0ESCCLK 49 71*4882a593Smuzhiyun #define PRCMU_DSI1ESCCLK 50 72*4882a593Smuzhiyun #define PRCMU_DSI2ESCCLK 51 73*4882a593Smuzhiyun 74*4882a593Smuzhiyun /* LCD DSI PLL - Ux540 only */ 75*4882a593Smuzhiyun #define PRCMU_PLLDSI_LCD 52 76*4882a593Smuzhiyun #define PRCMU_DSI0CLK_LCD 53 77*4882a593Smuzhiyun #define PRCMU_DSI1CLK_LCD 54 78*4882a593Smuzhiyun #define PRCMU_DSI0ESCCLK_LCD 55 79*4882a593Smuzhiyun #define PRCMU_DSI1ESCCLK_LCD 56 80*4882a593Smuzhiyun #define PRCMU_DSI2ESCCLK_LCD 57 81*4882a593Smuzhiyun 82*4882a593Smuzhiyun #define PRCMU_NUM_CLKS 58 83*4882a593Smuzhiyun 84*4882a593Smuzhiyun #endif 85