1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * This header provides macros for ams AS3722 device bindings. 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (c) 2013, NVIDIA Corporation. 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * Author: Laxman Dewangan <ldewangan@nvidia.com> 8*4882a593Smuzhiyun * 9*4882a593Smuzhiyun */ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #ifndef __DT_BINDINGS_AS3722_H__ 12*4882a593Smuzhiyun #define __DT_BINDINGS_AS3722_H__ 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun /* External control pins */ 15*4882a593Smuzhiyun #define AS3722_EXT_CONTROL_PIN_ENABLE1 1 16*4882a593Smuzhiyun #define AS3722_EXT_CONTROL_PIN_ENABLE2 2 17*4882a593Smuzhiyun #define AS3722_EXT_CONTROL_PIN_ENABLE3 3 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun /* Interrupt numbers for AS3722 */ 20*4882a593Smuzhiyun #define AS3722_IRQ_LID 0 21*4882a593Smuzhiyun #define AS3722_IRQ_ACOK 1 22*4882a593Smuzhiyun #define AS3722_IRQ_ENABLE1 2 23*4882a593Smuzhiyun #define AS3722_IRQ_OCCUR_ALARM_SD0 3 24*4882a593Smuzhiyun #define AS3722_IRQ_ONKEY_LONG_PRESS 4 25*4882a593Smuzhiyun #define AS3722_IRQ_ONKEY 5 26*4882a593Smuzhiyun #define AS3722_IRQ_OVTMP 6 27*4882a593Smuzhiyun #define AS3722_IRQ_LOWBAT 7 28*4882a593Smuzhiyun #define AS3722_IRQ_SD0_LV 8 29*4882a593Smuzhiyun #define AS3722_IRQ_SD1_LV 9 30*4882a593Smuzhiyun #define AS3722_IRQ_SD2_LV 10 31*4882a593Smuzhiyun #define AS3722_IRQ_PWM1_OV_PROT 11 32*4882a593Smuzhiyun #define AS3722_IRQ_PWM2_OV_PROT 12 33*4882a593Smuzhiyun #define AS3722_IRQ_ENABLE2 13 34*4882a593Smuzhiyun #define AS3722_IRQ_SD6_LV 14 35*4882a593Smuzhiyun #define AS3722_IRQ_RTC_REP 15 36*4882a593Smuzhiyun #define AS3722_IRQ_RTC_ALARM 16 37*4882a593Smuzhiyun #define AS3722_IRQ_GPIO1 17 38*4882a593Smuzhiyun #define AS3722_IRQ_GPIO2 18 39*4882a593Smuzhiyun #define AS3722_IRQ_GPIO3 19 40*4882a593Smuzhiyun #define AS3722_IRQ_GPIO4 20 41*4882a593Smuzhiyun #define AS3722_IRQ_GPIO5 21 42*4882a593Smuzhiyun #define AS3722_IRQ_WATCHDOG 22 43*4882a593Smuzhiyun #define AS3722_IRQ_ENABLE3 23 44*4882a593Smuzhiyun #define AS3722_IRQ_TEMP_SD0_SHUTDOWN 24 45*4882a593Smuzhiyun #define AS3722_IRQ_TEMP_SD1_SHUTDOWN 25 46*4882a593Smuzhiyun #define AS3722_IRQ_TEMP_SD2_SHUTDOWN 26 47*4882a593Smuzhiyun #define AS3722_IRQ_TEMP_SD0_ALARM 27 48*4882a593Smuzhiyun #define AS3722_IRQ_TEMP_SD1_ALARM 28 49*4882a593Smuzhiyun #define AS3722_IRQ_TEMP_SD6_ALARM 29 50*4882a593Smuzhiyun #define AS3722_IRQ_OCCUR_ALARM_SD6 30 51*4882a593Smuzhiyun #define AS3722_IRQ_ADC 31 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun #endif /* __DT_BINDINGS_AS3722_H__ */ 54