1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun #ifndef DT_BINDINGS_MEMORY_TEGRA210_MC_H 3*4882a593Smuzhiyun #define DT_BINDINGS_MEMORY_TEGRA210_MC_H 4*4882a593Smuzhiyun 5*4882a593Smuzhiyun #define TEGRA_SWGROUP_PTC 0 6*4882a593Smuzhiyun #define TEGRA_SWGROUP_DC 1 7*4882a593Smuzhiyun #define TEGRA_SWGROUP_DCB 2 8*4882a593Smuzhiyun #define TEGRA_SWGROUP_AFI 3 9*4882a593Smuzhiyun #define TEGRA_SWGROUP_AVPC 4 10*4882a593Smuzhiyun #define TEGRA_SWGROUP_HDA 5 11*4882a593Smuzhiyun #define TEGRA_SWGROUP_HC 6 12*4882a593Smuzhiyun #define TEGRA_SWGROUP_NVENC 7 13*4882a593Smuzhiyun #define TEGRA_SWGROUP_PPCS 8 14*4882a593Smuzhiyun #define TEGRA_SWGROUP_SATA 9 15*4882a593Smuzhiyun #define TEGRA_SWGROUP_MPCORE 10 16*4882a593Smuzhiyun #define TEGRA_SWGROUP_ISP2 11 17*4882a593Smuzhiyun #define TEGRA_SWGROUP_XUSB_HOST 12 18*4882a593Smuzhiyun #define TEGRA_SWGROUP_XUSB_DEV 13 19*4882a593Smuzhiyun #define TEGRA_SWGROUP_ISP2B 14 20*4882a593Smuzhiyun #define TEGRA_SWGROUP_TSEC 15 21*4882a593Smuzhiyun #define TEGRA_SWGROUP_A9AVP 16 22*4882a593Smuzhiyun #define TEGRA_SWGROUP_GPU 17 23*4882a593Smuzhiyun #define TEGRA_SWGROUP_SDMMC1A 18 24*4882a593Smuzhiyun #define TEGRA_SWGROUP_SDMMC2A 19 25*4882a593Smuzhiyun #define TEGRA_SWGROUP_SDMMC3A 20 26*4882a593Smuzhiyun #define TEGRA_SWGROUP_SDMMC4A 21 27*4882a593Smuzhiyun #define TEGRA_SWGROUP_VIC 22 28*4882a593Smuzhiyun #define TEGRA_SWGROUP_VI 23 29*4882a593Smuzhiyun #define TEGRA_SWGROUP_NVDEC 24 30*4882a593Smuzhiyun #define TEGRA_SWGROUP_APE 25 31*4882a593Smuzhiyun #define TEGRA_SWGROUP_NVJPG 26 32*4882a593Smuzhiyun #define TEGRA_SWGROUP_SE 27 33*4882a593Smuzhiyun #define TEGRA_SWGROUP_AXIAP 28 34*4882a593Smuzhiyun #define TEGRA_SWGROUP_ETR 29 35*4882a593Smuzhiyun #define TEGRA_SWGROUP_TSECB 30 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun #define TEGRA210_MC_RESET_AFI 0 38*4882a593Smuzhiyun #define TEGRA210_MC_RESET_AVPC 1 39*4882a593Smuzhiyun #define TEGRA210_MC_RESET_DC 2 40*4882a593Smuzhiyun #define TEGRA210_MC_RESET_DCB 3 41*4882a593Smuzhiyun #define TEGRA210_MC_RESET_HC 4 42*4882a593Smuzhiyun #define TEGRA210_MC_RESET_HDA 5 43*4882a593Smuzhiyun #define TEGRA210_MC_RESET_ISP2 6 44*4882a593Smuzhiyun #define TEGRA210_MC_RESET_MPCORE 7 45*4882a593Smuzhiyun #define TEGRA210_MC_RESET_NVENC 8 46*4882a593Smuzhiyun #define TEGRA210_MC_RESET_PPCS 9 47*4882a593Smuzhiyun #define TEGRA210_MC_RESET_SATA 10 48*4882a593Smuzhiyun #define TEGRA210_MC_RESET_VI 11 49*4882a593Smuzhiyun #define TEGRA210_MC_RESET_VIC 12 50*4882a593Smuzhiyun #define TEGRA210_MC_RESET_XUSB_HOST 13 51*4882a593Smuzhiyun #define TEGRA210_MC_RESET_XUSB_DEV 14 52*4882a593Smuzhiyun #define TEGRA210_MC_RESET_A9AVP 15 53*4882a593Smuzhiyun #define TEGRA210_MC_RESET_TSEC 16 54*4882a593Smuzhiyun #define TEGRA210_MC_RESET_SDMMC1 17 55*4882a593Smuzhiyun #define TEGRA210_MC_RESET_SDMMC2 18 56*4882a593Smuzhiyun #define TEGRA210_MC_RESET_SDMMC3 19 57*4882a593Smuzhiyun #define TEGRA210_MC_RESET_SDMMC4 20 58*4882a593Smuzhiyun #define TEGRA210_MC_RESET_ISP2B 21 59*4882a593Smuzhiyun #define TEGRA210_MC_RESET_GPU 22 60*4882a593Smuzhiyun #define TEGRA210_MC_RESET_NVDEC 23 61*4882a593Smuzhiyun #define TEGRA210_MC_RESET_APE 24 62*4882a593Smuzhiyun #define TEGRA210_MC_RESET_SE 25 63*4882a593Smuzhiyun #define TEGRA210_MC_RESET_NVJPG 26 64*4882a593Smuzhiyun #define TEGRA210_MC_RESET_AXIAP 27 65*4882a593Smuzhiyun #define TEGRA210_MC_RESET_ETR 28 66*4882a593Smuzhiyun #define TEGRA210_MC_RESET_TSECB 29 67*4882a593Smuzhiyun 68*4882a593Smuzhiyun #endif 69