1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun #ifndef DT_BINDINGS_MEMORY_TEGRA20_MC_H 3*4882a593Smuzhiyun #define DT_BINDINGS_MEMORY_TEGRA20_MC_H 4*4882a593Smuzhiyun 5*4882a593Smuzhiyun #define TEGRA20_MC_RESET_AVPC 0 6*4882a593Smuzhiyun #define TEGRA20_MC_RESET_DC 1 7*4882a593Smuzhiyun #define TEGRA20_MC_RESET_DCB 2 8*4882a593Smuzhiyun #define TEGRA20_MC_RESET_EPP 3 9*4882a593Smuzhiyun #define TEGRA20_MC_RESET_2D 4 10*4882a593Smuzhiyun #define TEGRA20_MC_RESET_HC 5 11*4882a593Smuzhiyun #define TEGRA20_MC_RESET_ISP 6 12*4882a593Smuzhiyun #define TEGRA20_MC_RESET_MPCORE 7 13*4882a593Smuzhiyun #define TEGRA20_MC_RESET_MPEA 8 14*4882a593Smuzhiyun #define TEGRA20_MC_RESET_MPEB 9 15*4882a593Smuzhiyun #define TEGRA20_MC_RESET_MPEC 10 16*4882a593Smuzhiyun #define TEGRA20_MC_RESET_3D 11 17*4882a593Smuzhiyun #define TEGRA20_MC_RESET_PPCS 12 18*4882a593Smuzhiyun #define TEGRA20_MC_RESET_VDE 13 19*4882a593Smuzhiyun #define TEGRA20_MC_RESET_VI 14 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun #endif 22