1*4882a593Smuzhiyun #ifndef DT_BINDINGS_MEMORY_TEGRA194_MC_H 2*4882a593Smuzhiyun #define DT_BINDINGS_MEMORY_TEGRA194_MC_H 3*4882a593Smuzhiyun 4*4882a593Smuzhiyun /* special clients */ 5*4882a593Smuzhiyun #define TEGRA194_SID_INVALID 0x00 6*4882a593Smuzhiyun #define TEGRA194_SID_PASSTHROUGH 0x7f 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun /* host1x clients */ 9*4882a593Smuzhiyun #define TEGRA194_SID_HOST1X 0x01 10*4882a593Smuzhiyun #define TEGRA194_SID_CSI 0x02 11*4882a593Smuzhiyun #define TEGRA194_SID_VIC 0x03 12*4882a593Smuzhiyun #define TEGRA194_SID_VI 0x04 13*4882a593Smuzhiyun #define TEGRA194_SID_ISP 0x05 14*4882a593Smuzhiyun #define TEGRA194_SID_NVDEC 0x06 15*4882a593Smuzhiyun #define TEGRA194_SID_NVENC 0x07 16*4882a593Smuzhiyun #define TEGRA194_SID_NVJPG 0x08 17*4882a593Smuzhiyun #define TEGRA194_SID_NVDISPLAY 0x09 18*4882a593Smuzhiyun #define TEGRA194_SID_TSEC 0x0a 19*4882a593Smuzhiyun #define TEGRA194_SID_TSECB 0x0b 20*4882a593Smuzhiyun #define TEGRA194_SID_SE 0x0c 21*4882a593Smuzhiyun #define TEGRA194_SID_SE1 0x0d 22*4882a593Smuzhiyun #define TEGRA194_SID_SE2 0x0e 23*4882a593Smuzhiyun #define TEGRA194_SID_SE3 0x0f 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun /* GPU clients */ 26*4882a593Smuzhiyun #define TEGRA194_SID_GPU 0x10 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun /* other SoC clients */ 29*4882a593Smuzhiyun #define TEGRA194_SID_AFI 0x11 30*4882a593Smuzhiyun #define TEGRA194_SID_HDA 0x12 31*4882a593Smuzhiyun #define TEGRA194_SID_ETR 0x13 32*4882a593Smuzhiyun #define TEGRA194_SID_EQOS 0x14 33*4882a593Smuzhiyun #define TEGRA194_SID_UFSHC 0x15 34*4882a593Smuzhiyun #define TEGRA194_SID_AON 0x16 35*4882a593Smuzhiyun #define TEGRA194_SID_SDMMC4 0x17 36*4882a593Smuzhiyun #define TEGRA194_SID_SDMMC3 0x18 37*4882a593Smuzhiyun #define TEGRA194_SID_SDMMC2 0x19 38*4882a593Smuzhiyun #define TEGRA194_SID_SDMMC1 0x1a 39*4882a593Smuzhiyun #define TEGRA194_SID_XUSB_HOST 0x1b 40*4882a593Smuzhiyun #define TEGRA194_SID_XUSB_DEV 0x1c 41*4882a593Smuzhiyun #define TEGRA194_SID_SATA 0x1d 42*4882a593Smuzhiyun #define TEGRA194_SID_APE 0x1e 43*4882a593Smuzhiyun #define TEGRA194_SID_SCE 0x1f 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun /* GPC DMA clients */ 46*4882a593Smuzhiyun #define TEGRA194_SID_GPCDMA_0 0x20 47*4882a593Smuzhiyun #define TEGRA194_SID_GPCDMA_1 0x21 48*4882a593Smuzhiyun #define TEGRA194_SID_GPCDMA_2 0x22 49*4882a593Smuzhiyun #define TEGRA194_SID_GPCDMA_3 0x23 50*4882a593Smuzhiyun #define TEGRA194_SID_GPCDMA_4 0x24 51*4882a593Smuzhiyun #define TEGRA194_SID_GPCDMA_5 0x25 52*4882a593Smuzhiyun #define TEGRA194_SID_GPCDMA_6 0x26 53*4882a593Smuzhiyun #define TEGRA194_SID_GPCDMA_7 0x27 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun /* APE DMA clients */ 56*4882a593Smuzhiyun #define TEGRA194_SID_APE_1 0x28 57*4882a593Smuzhiyun #define TEGRA194_SID_APE_2 0x29 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun /* camera RTCPU */ 60*4882a593Smuzhiyun #define TEGRA194_SID_RCE 0x2a 61*4882a593Smuzhiyun 62*4882a593Smuzhiyun /* camera RTCPU on host1x address space */ 63*4882a593Smuzhiyun #define TEGRA194_SID_RCE_1X 0x2b 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun /* APE DMA clients */ 66*4882a593Smuzhiyun #define TEGRA194_SID_APE_3 0x2c 67*4882a593Smuzhiyun 68*4882a593Smuzhiyun /* camera RTCPU running on APE */ 69*4882a593Smuzhiyun #define TEGRA194_SID_APE_CAM 0x2d 70*4882a593Smuzhiyun #define TEGRA194_SID_APE_CAM_1X 0x2e 71*4882a593Smuzhiyun 72*4882a593Smuzhiyun #define TEGRA194_SID_RCE_RM 0x2f 73*4882a593Smuzhiyun #define TEGRA194_SID_VI_FALCON 0x30 74*4882a593Smuzhiyun #define TEGRA194_SID_ISP_FALCON 0x31 75*4882a593Smuzhiyun 76*4882a593Smuzhiyun /* 77*4882a593Smuzhiyun * The BPMP has its SID value hardcoded in the firmware. Changing it requires 78*4882a593Smuzhiyun * considerable effort. 79*4882a593Smuzhiyun */ 80*4882a593Smuzhiyun #define TEGRA194_SID_BPMP 0x32 81*4882a593Smuzhiyun 82*4882a593Smuzhiyun /* for SMMU tests */ 83*4882a593Smuzhiyun #define TEGRA194_SID_SMMU_TEST 0x33 84*4882a593Smuzhiyun 85*4882a593Smuzhiyun /* host1x virtualization channels */ 86*4882a593Smuzhiyun #define TEGRA194_SID_HOST1X_CTX0 0x38 87*4882a593Smuzhiyun #define TEGRA194_SID_HOST1X_CTX1 0x39 88*4882a593Smuzhiyun #define TEGRA194_SID_HOST1X_CTX2 0x3a 89*4882a593Smuzhiyun #define TEGRA194_SID_HOST1X_CTX3 0x3b 90*4882a593Smuzhiyun #define TEGRA194_SID_HOST1X_CTX4 0x3c 91*4882a593Smuzhiyun #define TEGRA194_SID_HOST1X_CTX5 0x3d 92*4882a593Smuzhiyun #define TEGRA194_SID_HOST1X_CTX6 0x3e 93*4882a593Smuzhiyun #define TEGRA194_SID_HOST1X_CTX7 0x3f 94*4882a593Smuzhiyun 95*4882a593Smuzhiyun /* host1x command buffers */ 96*4882a593Smuzhiyun #define TEGRA194_SID_HOST1X_VM0 0x40 97*4882a593Smuzhiyun #define TEGRA194_SID_HOST1X_VM1 0x41 98*4882a593Smuzhiyun #define TEGRA194_SID_HOST1X_VM2 0x42 99*4882a593Smuzhiyun #define TEGRA194_SID_HOST1X_VM3 0x43 100*4882a593Smuzhiyun #define TEGRA194_SID_HOST1X_VM4 0x44 101*4882a593Smuzhiyun #define TEGRA194_SID_HOST1X_VM5 0x45 102*4882a593Smuzhiyun #define TEGRA194_SID_HOST1X_VM6 0x46 103*4882a593Smuzhiyun #define TEGRA194_SID_HOST1X_VM7 0x47 104*4882a593Smuzhiyun 105*4882a593Smuzhiyun /* SE data buffers */ 106*4882a593Smuzhiyun #define TEGRA194_SID_SE_VM0 0x48 107*4882a593Smuzhiyun #define TEGRA194_SID_SE_VM1 0x49 108*4882a593Smuzhiyun #define TEGRA194_SID_SE_VM2 0x4a 109*4882a593Smuzhiyun #define TEGRA194_SID_SE_VM3 0x4b 110*4882a593Smuzhiyun #define TEGRA194_SID_SE_VM4 0x4c 111*4882a593Smuzhiyun #define TEGRA194_SID_SE_VM5 0x4d 112*4882a593Smuzhiyun #define TEGRA194_SID_SE_VM6 0x4e 113*4882a593Smuzhiyun #define TEGRA194_SID_SE_VM7 0x4f 114*4882a593Smuzhiyun 115*4882a593Smuzhiyun #define TEGRA194_SID_MIU 0x50 116*4882a593Smuzhiyun 117*4882a593Smuzhiyun #define TEGRA194_SID_NVDLA0 0x51 118*4882a593Smuzhiyun #define TEGRA194_SID_NVDLA1 0x52 119*4882a593Smuzhiyun 120*4882a593Smuzhiyun #define TEGRA194_SID_PVA0 0x53 121*4882a593Smuzhiyun #define TEGRA194_SID_PVA1 0x54 122*4882a593Smuzhiyun #define TEGRA194_SID_NVENC1 0x55 123*4882a593Smuzhiyun #define TEGRA194_SID_PCIE0 0x56 124*4882a593Smuzhiyun #define TEGRA194_SID_PCIE1 0x57 125*4882a593Smuzhiyun #define TEGRA194_SID_PCIE2 0x58 126*4882a593Smuzhiyun #define TEGRA194_SID_PCIE3 0x59 127*4882a593Smuzhiyun #define TEGRA194_SID_PCIE4 0x5a 128*4882a593Smuzhiyun #define TEGRA194_SID_PCIE5 0x5b 129*4882a593Smuzhiyun #define TEGRA194_SID_NVDEC1 0x5c 130*4882a593Smuzhiyun 131*4882a593Smuzhiyun #define TEGRA194_SID_XUSB_VF0 0x5d 132*4882a593Smuzhiyun #define TEGRA194_SID_XUSB_VF1 0x5e 133*4882a593Smuzhiyun #define TEGRA194_SID_XUSB_VF2 0x5f 134*4882a593Smuzhiyun #define TEGRA194_SID_XUSB_VF3 0x60 135*4882a593Smuzhiyun 136*4882a593Smuzhiyun #define TEGRA194_SID_RCE_VM3 0x61 137*4882a593Smuzhiyun #define TEGRA194_SID_VI_VM2 0x62 138*4882a593Smuzhiyun #define TEGRA194_SID_VI_VM3 0x63 139*4882a593Smuzhiyun #define TEGRA194_SID_RCE_SERVER 0x64 140*4882a593Smuzhiyun 141*4882a593Smuzhiyun /* 142*4882a593Smuzhiyun * memory client IDs 143*4882a593Smuzhiyun */ 144*4882a593Smuzhiyun 145*4882a593Smuzhiyun /* Misses from System Memory Management Unit (SMMU) Page Table Cache (PTC) */ 146*4882a593Smuzhiyun #define TEGRA194_MEMORY_CLIENT_PTCR 0x00 147*4882a593Smuzhiyun /* MSS internal memqual MIU7 read clients */ 148*4882a593Smuzhiyun #define TEGRA194_MEMORY_CLIENT_MIU7R 0x01 149*4882a593Smuzhiyun /* MSS internal memqual MIU7 write clients */ 150*4882a593Smuzhiyun #define TEGRA194_MEMORY_CLIENT_MIU7W 0x02 151*4882a593Smuzhiyun /* High-definition audio (HDA) read clients */ 152*4882a593Smuzhiyun #define TEGRA194_MEMORY_CLIENT_HDAR 0x15 153*4882a593Smuzhiyun /* Host channel data read clients */ 154*4882a593Smuzhiyun #define TEGRA194_MEMORY_CLIENT_HOST1XDMAR 0x16 155*4882a593Smuzhiyun #define TEGRA194_MEMORY_CLIENT_NVENCSRD 0x1c 156*4882a593Smuzhiyun /* SATA read clients */ 157*4882a593Smuzhiyun #define TEGRA194_MEMORY_CLIENT_SATAR 0x1f 158*4882a593Smuzhiyun /* Reads from Cortex-A9 4 CPU cores via the L2 cache */ 159*4882a593Smuzhiyun #define TEGRA194_MEMORY_CLIENT_MPCORER 0x27 160*4882a593Smuzhiyun #define TEGRA194_MEMORY_CLIENT_NVENCSWR 0x2b 161*4882a593Smuzhiyun /* High-definition audio (HDA) write clients */ 162*4882a593Smuzhiyun #define TEGRA194_MEMORY_CLIENT_HDAW 0x35 163*4882a593Smuzhiyun /* Writes from Cortex-A9 4 CPU cores via the L2 cache */ 164*4882a593Smuzhiyun #define TEGRA194_MEMORY_CLIENT_MPCOREW 0x39 165*4882a593Smuzhiyun /* SATA write clients */ 166*4882a593Smuzhiyun #define TEGRA194_MEMORY_CLIENT_SATAW 0x3d 167*4882a593Smuzhiyun /* ISP read client for Crossbar A */ 168*4882a593Smuzhiyun #define TEGRA194_MEMORY_CLIENT_ISPRA 0x44 169*4882a593Smuzhiyun /* ISP read client 1 for Crossbar A */ 170*4882a593Smuzhiyun #define TEGRA194_MEMORY_CLIENT_ISPFALR 0x45 171*4882a593Smuzhiyun /* ISP Write client for Crossbar A */ 172*4882a593Smuzhiyun #define TEGRA194_MEMORY_CLIENT_ISPWA 0x46 173*4882a593Smuzhiyun /* ISP Write client Crossbar B */ 174*4882a593Smuzhiyun #define TEGRA194_MEMORY_CLIENT_ISPWB 0x47 175*4882a593Smuzhiyun /* XUSB_HOST read clients */ 176*4882a593Smuzhiyun #define TEGRA194_MEMORY_CLIENT_XUSB_HOSTR 0x4a 177*4882a593Smuzhiyun /* XUSB_HOST write clients */ 178*4882a593Smuzhiyun #define TEGRA194_MEMORY_CLIENT_XUSB_HOSTW 0x4b 179*4882a593Smuzhiyun /* XUSB read clients */ 180*4882a593Smuzhiyun #define TEGRA194_MEMORY_CLIENT_XUSB_DEVR 0x4c 181*4882a593Smuzhiyun /* XUSB_DEV write clients */ 182*4882a593Smuzhiyun #define TEGRA194_MEMORY_CLIENT_XUSB_DEVW 0x4d 183*4882a593Smuzhiyun /* sdmmca memory read client */ 184*4882a593Smuzhiyun #define TEGRA194_MEMORY_CLIENT_SDMMCRA 0x60 185*4882a593Smuzhiyun /* sdmmc memory read client */ 186*4882a593Smuzhiyun #define TEGRA194_MEMORY_CLIENT_SDMMCR 0x62 187*4882a593Smuzhiyun /* sdmmcd memory read client */ 188*4882a593Smuzhiyun #define TEGRA194_MEMORY_CLIENT_SDMMCRAB 0x63 189*4882a593Smuzhiyun /* sdmmca memory write client */ 190*4882a593Smuzhiyun #define TEGRA194_MEMORY_CLIENT_SDMMCWA 0x64 191*4882a593Smuzhiyun /* sdmmc memory write client */ 192*4882a593Smuzhiyun #define TEGRA194_MEMORY_CLIENT_SDMMCW 0x66 193*4882a593Smuzhiyun /* sdmmcd memory write client */ 194*4882a593Smuzhiyun #define TEGRA194_MEMORY_CLIENT_SDMMCWAB 0x67 195*4882a593Smuzhiyun #define TEGRA194_MEMORY_CLIENT_VICSRD 0x6c 196*4882a593Smuzhiyun #define TEGRA194_MEMORY_CLIENT_VICSWR 0x6d 197*4882a593Smuzhiyun /* VI Write client */ 198*4882a593Smuzhiyun #define TEGRA194_MEMORY_CLIENT_VIW 0x72 199*4882a593Smuzhiyun #define TEGRA194_MEMORY_CLIENT_NVDECSRD 0x78 200*4882a593Smuzhiyun #define TEGRA194_MEMORY_CLIENT_NVDECSWR 0x79 201*4882a593Smuzhiyun /* Audio Processing (APE) engine read clients */ 202*4882a593Smuzhiyun #define TEGRA194_MEMORY_CLIENT_APER 0x7a 203*4882a593Smuzhiyun /* Audio Processing (APE) engine write clients */ 204*4882a593Smuzhiyun #define TEGRA194_MEMORY_CLIENT_APEW 0x7b 205*4882a593Smuzhiyun #define TEGRA194_MEMORY_CLIENT_NVJPGSRD 0x7e 206*4882a593Smuzhiyun #define TEGRA194_MEMORY_CLIENT_NVJPGSWR 0x7f 207*4882a593Smuzhiyun /* AXI AP and DFD-AUX0/1 read clients Both share the same interface on the on MSS */ 208*4882a593Smuzhiyun #define TEGRA194_MEMORY_CLIENT_AXIAPR 0x82 209*4882a593Smuzhiyun /* AXI AP and DFD-AUX0/1 write clients Both sahre the same interface on MSS */ 210*4882a593Smuzhiyun #define TEGRA194_MEMORY_CLIENT_AXIAPW 0x83 211*4882a593Smuzhiyun /* ETR read clients */ 212*4882a593Smuzhiyun #define TEGRA194_MEMORY_CLIENT_ETRR 0x84 213*4882a593Smuzhiyun /* ETR write clients */ 214*4882a593Smuzhiyun #define TEGRA194_MEMORY_CLIENT_ETRW 0x85 215*4882a593Smuzhiyun /* AXI Switch read client */ 216*4882a593Smuzhiyun #define TEGRA194_MEMORY_CLIENT_AXISR 0x8c 217*4882a593Smuzhiyun /* AXI Switch write client */ 218*4882a593Smuzhiyun #define TEGRA194_MEMORY_CLIENT_AXISW 0x8d 219*4882a593Smuzhiyun /* EQOS read client */ 220*4882a593Smuzhiyun #define TEGRA194_MEMORY_CLIENT_EQOSR 0x8e 221*4882a593Smuzhiyun /* EQOS write client */ 222*4882a593Smuzhiyun #define TEGRA194_MEMORY_CLIENT_EQOSW 0x8f 223*4882a593Smuzhiyun /* UFSHC read client */ 224*4882a593Smuzhiyun #define TEGRA194_MEMORY_CLIENT_UFSHCR 0x90 225*4882a593Smuzhiyun /* UFSHC write client */ 226*4882a593Smuzhiyun #define TEGRA194_MEMORY_CLIENT_UFSHCW 0x91 227*4882a593Smuzhiyun /* NVDISPLAY read client */ 228*4882a593Smuzhiyun #define TEGRA194_MEMORY_CLIENT_NVDISPLAYR 0x92 229*4882a593Smuzhiyun /* BPMP read client */ 230*4882a593Smuzhiyun #define TEGRA194_MEMORY_CLIENT_BPMPR 0x93 231*4882a593Smuzhiyun /* BPMP write client */ 232*4882a593Smuzhiyun #define TEGRA194_MEMORY_CLIENT_BPMPW 0x94 233*4882a593Smuzhiyun /* BPMPDMA read client */ 234*4882a593Smuzhiyun #define TEGRA194_MEMORY_CLIENT_BPMPDMAR 0x95 235*4882a593Smuzhiyun /* BPMPDMA write client */ 236*4882a593Smuzhiyun #define TEGRA194_MEMORY_CLIENT_BPMPDMAW 0x96 237*4882a593Smuzhiyun /* AON read client */ 238*4882a593Smuzhiyun #define TEGRA194_MEMORY_CLIENT_AONR 0x97 239*4882a593Smuzhiyun /* AON write client */ 240*4882a593Smuzhiyun #define TEGRA194_MEMORY_CLIENT_AONW 0x98 241*4882a593Smuzhiyun /* AONDMA read client */ 242*4882a593Smuzhiyun #define TEGRA194_MEMORY_CLIENT_AONDMAR 0x99 243*4882a593Smuzhiyun /* AONDMA write client */ 244*4882a593Smuzhiyun #define TEGRA194_MEMORY_CLIENT_AONDMAW 0x9a 245*4882a593Smuzhiyun /* SCE read client */ 246*4882a593Smuzhiyun #define TEGRA194_MEMORY_CLIENT_SCER 0x9b 247*4882a593Smuzhiyun /* SCE write client */ 248*4882a593Smuzhiyun #define TEGRA194_MEMORY_CLIENT_SCEW 0x9c 249*4882a593Smuzhiyun /* SCEDMA read client */ 250*4882a593Smuzhiyun #define TEGRA194_MEMORY_CLIENT_SCEDMAR 0x9d 251*4882a593Smuzhiyun /* SCEDMA write client */ 252*4882a593Smuzhiyun #define TEGRA194_MEMORY_CLIENT_SCEDMAW 0x9e 253*4882a593Smuzhiyun /* APEDMA read client */ 254*4882a593Smuzhiyun #define TEGRA194_MEMORY_CLIENT_APEDMAR 0x9f 255*4882a593Smuzhiyun /* APEDMA write client */ 256*4882a593Smuzhiyun #define TEGRA194_MEMORY_CLIENT_APEDMAW 0xa0 257*4882a593Smuzhiyun /* NVDISPLAY read client instance 2 */ 258*4882a593Smuzhiyun #define TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 0xa1 259*4882a593Smuzhiyun #define TEGRA194_MEMORY_CLIENT_VICSRD1 0xa2 260*4882a593Smuzhiyun #define TEGRA194_MEMORY_CLIENT_NVDECSRD1 0xa3 261*4882a593Smuzhiyun /* MSS internal memqual MIU0 read clients */ 262*4882a593Smuzhiyun #define TEGRA194_MEMORY_CLIENT_MIU0R 0xa6 263*4882a593Smuzhiyun /* MSS internal memqual MIU0 write clients */ 264*4882a593Smuzhiyun #define TEGRA194_MEMORY_CLIENT_MIU0W 0xa7 265*4882a593Smuzhiyun /* MSS internal memqual MIU1 read clients */ 266*4882a593Smuzhiyun #define TEGRA194_MEMORY_CLIENT_MIU1R 0xa8 267*4882a593Smuzhiyun /* MSS internal memqual MIU1 write clients */ 268*4882a593Smuzhiyun #define TEGRA194_MEMORY_CLIENT_MIU1W 0xa9 269*4882a593Smuzhiyun /* MSS internal memqual MIU2 read clients */ 270*4882a593Smuzhiyun #define TEGRA194_MEMORY_CLIENT_MIU2R 0xae 271*4882a593Smuzhiyun /* MSS internal memqual MIU2 write clients */ 272*4882a593Smuzhiyun #define TEGRA194_MEMORY_CLIENT_MIU2W 0xaf 273*4882a593Smuzhiyun /* MSS internal memqual MIU3 read clients */ 274*4882a593Smuzhiyun #define TEGRA194_MEMORY_CLIENT_MIU3R 0xb0 275*4882a593Smuzhiyun /* MSS internal memqual MIU3 write clients */ 276*4882a593Smuzhiyun #define TEGRA194_MEMORY_CLIENT_MIU3W 0xb1 277*4882a593Smuzhiyun /* MSS internal memqual MIU4 read clients */ 278*4882a593Smuzhiyun #define TEGRA194_MEMORY_CLIENT_MIU4R 0xb2 279*4882a593Smuzhiyun /* MSS internal memqual MIU4 write clients */ 280*4882a593Smuzhiyun #define TEGRA194_MEMORY_CLIENT_MIU4W 0xb3 281*4882a593Smuzhiyun #define TEGRA194_MEMORY_CLIENT_DPMUR 0xb4 282*4882a593Smuzhiyun #define TEGRA194_MEMORY_CLIENT_DPMUW 0xb5 283*4882a593Smuzhiyun #define TEGRA194_MEMORY_CLIENT_NVL0R 0xb6 284*4882a593Smuzhiyun #define TEGRA194_MEMORY_CLIENT_NVL0W 0xb7 285*4882a593Smuzhiyun #define TEGRA194_MEMORY_CLIENT_NVL1R 0xb8 286*4882a593Smuzhiyun #define TEGRA194_MEMORY_CLIENT_NVL1W 0xb9 287*4882a593Smuzhiyun #define TEGRA194_MEMORY_CLIENT_NVL2R 0xba 288*4882a593Smuzhiyun #define TEGRA194_MEMORY_CLIENT_NVL2W 0xbb 289*4882a593Smuzhiyun /* VI FLACON read clients */ 290*4882a593Smuzhiyun #define TEGRA194_MEMORY_CLIENT_VIFALR 0xbc 291*4882a593Smuzhiyun /* VIFAL write clients */ 292*4882a593Smuzhiyun #define TEGRA194_MEMORY_CLIENT_VIFALW 0xbd 293*4882a593Smuzhiyun /* DLA0ARDA read clients */ 294*4882a593Smuzhiyun #define TEGRA194_MEMORY_CLIENT_DLA0RDA 0xbe 295*4882a593Smuzhiyun /* DLA0 Falcon read clients */ 296*4882a593Smuzhiyun #define TEGRA194_MEMORY_CLIENT_DLA0FALRDB 0xbf 297*4882a593Smuzhiyun /* DLA0 write clients */ 298*4882a593Smuzhiyun #define TEGRA194_MEMORY_CLIENT_DLA0WRA 0xc0 299*4882a593Smuzhiyun /* DLA0 write clients */ 300*4882a593Smuzhiyun #define TEGRA194_MEMORY_CLIENT_DLA0FALWRB 0xc1 301*4882a593Smuzhiyun /* DLA1ARDA read clients */ 302*4882a593Smuzhiyun #define TEGRA194_MEMORY_CLIENT_DLA1RDA 0xc2 303*4882a593Smuzhiyun /* DLA1 Falcon read clients */ 304*4882a593Smuzhiyun #define TEGRA194_MEMORY_CLIENT_DLA1FALRDB 0xc3 305*4882a593Smuzhiyun /* DLA1 write clients */ 306*4882a593Smuzhiyun #define TEGRA194_MEMORY_CLIENT_DLA1WRA 0xc4 307*4882a593Smuzhiyun /* DLA1 write clients */ 308*4882a593Smuzhiyun #define TEGRA194_MEMORY_CLIENT_DLA1FALWRB 0xc5 309*4882a593Smuzhiyun /* PVA0RDA read clients */ 310*4882a593Smuzhiyun #define TEGRA194_MEMORY_CLIENT_PVA0RDA 0xc6 311*4882a593Smuzhiyun /* PVA0RDB read clients */ 312*4882a593Smuzhiyun #define TEGRA194_MEMORY_CLIENT_PVA0RDB 0xc7 313*4882a593Smuzhiyun /* PVA0RDC read clients */ 314*4882a593Smuzhiyun #define TEGRA194_MEMORY_CLIENT_PVA0RDC 0xc8 315*4882a593Smuzhiyun /* PVA0WRA write clients */ 316*4882a593Smuzhiyun #define TEGRA194_MEMORY_CLIENT_PVA0WRA 0xc9 317*4882a593Smuzhiyun /* PVA0WRB write clients */ 318*4882a593Smuzhiyun #define TEGRA194_MEMORY_CLIENT_PVA0WRB 0xca 319*4882a593Smuzhiyun /* PVA0WRC write clients */ 320*4882a593Smuzhiyun #define TEGRA194_MEMORY_CLIENT_PVA0WRC 0xcb 321*4882a593Smuzhiyun /* PVA1RDA read clients */ 322*4882a593Smuzhiyun #define TEGRA194_MEMORY_CLIENT_PVA1RDA 0xcc 323*4882a593Smuzhiyun /* PVA1RDB read clients */ 324*4882a593Smuzhiyun #define TEGRA194_MEMORY_CLIENT_PVA1RDB 0xcd 325*4882a593Smuzhiyun /* PVA1RDC read clients */ 326*4882a593Smuzhiyun #define TEGRA194_MEMORY_CLIENT_PVA1RDC 0xce 327*4882a593Smuzhiyun /* PVA1WRA write clients */ 328*4882a593Smuzhiyun #define TEGRA194_MEMORY_CLIENT_PVA1WRA 0xcf 329*4882a593Smuzhiyun /* PVA1WRB write clients */ 330*4882a593Smuzhiyun #define TEGRA194_MEMORY_CLIENT_PVA1WRB 0xd0 331*4882a593Smuzhiyun /* PVA1WRC write clients */ 332*4882a593Smuzhiyun #define TEGRA194_MEMORY_CLIENT_PVA1WRC 0xd1 333*4882a593Smuzhiyun /* RCE read client */ 334*4882a593Smuzhiyun #define TEGRA194_MEMORY_CLIENT_RCER 0xd2 335*4882a593Smuzhiyun /* RCE write client */ 336*4882a593Smuzhiyun #define TEGRA194_MEMORY_CLIENT_RCEW 0xd3 337*4882a593Smuzhiyun /* RCEDMA read client */ 338*4882a593Smuzhiyun #define TEGRA194_MEMORY_CLIENT_RCEDMAR 0xd4 339*4882a593Smuzhiyun /* RCEDMA write client */ 340*4882a593Smuzhiyun #define TEGRA194_MEMORY_CLIENT_RCEDMAW 0xd5 341*4882a593Smuzhiyun #define TEGRA194_MEMORY_CLIENT_NVENC1SRD 0xd6 342*4882a593Smuzhiyun #define TEGRA194_MEMORY_CLIENT_NVENC1SWR 0xd7 343*4882a593Smuzhiyun /* PCIE0 read clients */ 344*4882a593Smuzhiyun #define TEGRA194_MEMORY_CLIENT_PCIE0R 0xd8 345*4882a593Smuzhiyun /* PCIE0 write clients */ 346*4882a593Smuzhiyun #define TEGRA194_MEMORY_CLIENT_PCIE0W 0xd9 347*4882a593Smuzhiyun /* PCIE1 read clients */ 348*4882a593Smuzhiyun #define TEGRA194_MEMORY_CLIENT_PCIE1R 0xda 349*4882a593Smuzhiyun /* PCIE1 write clients */ 350*4882a593Smuzhiyun #define TEGRA194_MEMORY_CLIENT_PCIE1W 0xdb 351*4882a593Smuzhiyun /* PCIE2 read clients */ 352*4882a593Smuzhiyun #define TEGRA194_MEMORY_CLIENT_PCIE2AR 0xdc 353*4882a593Smuzhiyun /* PCIE2 write clients */ 354*4882a593Smuzhiyun #define TEGRA194_MEMORY_CLIENT_PCIE2AW 0xdd 355*4882a593Smuzhiyun /* PCIE3 read clients */ 356*4882a593Smuzhiyun #define TEGRA194_MEMORY_CLIENT_PCIE3R 0xde 357*4882a593Smuzhiyun /* PCIE3 write clients */ 358*4882a593Smuzhiyun #define TEGRA194_MEMORY_CLIENT_PCIE3W 0xdf 359*4882a593Smuzhiyun /* PCIE4 read clients */ 360*4882a593Smuzhiyun #define TEGRA194_MEMORY_CLIENT_PCIE4R 0xe0 361*4882a593Smuzhiyun /* PCIE4 write clients */ 362*4882a593Smuzhiyun #define TEGRA194_MEMORY_CLIENT_PCIE4W 0xe1 363*4882a593Smuzhiyun /* PCIE5 read clients */ 364*4882a593Smuzhiyun #define TEGRA194_MEMORY_CLIENT_PCIE5R 0xe2 365*4882a593Smuzhiyun /* PCIE5 write clients */ 366*4882a593Smuzhiyun #define TEGRA194_MEMORY_CLIENT_PCIE5W 0xe3 367*4882a593Smuzhiyun /* ISP read client 1 for Crossbar A */ 368*4882a593Smuzhiyun #define TEGRA194_MEMORY_CLIENT_ISPFALW 0xe4 369*4882a593Smuzhiyun #define TEGRA194_MEMORY_CLIENT_NVL3R 0xe5 370*4882a593Smuzhiyun #define TEGRA194_MEMORY_CLIENT_NVL3W 0xe6 371*4882a593Smuzhiyun #define TEGRA194_MEMORY_CLIENT_NVL4R 0xe7 372*4882a593Smuzhiyun #define TEGRA194_MEMORY_CLIENT_NVL4W 0xe8 373*4882a593Smuzhiyun /* DLA0ARDA1 read clients */ 374*4882a593Smuzhiyun #define TEGRA194_MEMORY_CLIENT_DLA0RDA1 0xe9 375*4882a593Smuzhiyun /* DLA1ARDA1 read clients */ 376*4882a593Smuzhiyun #define TEGRA194_MEMORY_CLIENT_DLA1RDA1 0xea 377*4882a593Smuzhiyun /* PVA0RDA1 read clients */ 378*4882a593Smuzhiyun #define TEGRA194_MEMORY_CLIENT_PVA0RDA1 0xeb 379*4882a593Smuzhiyun /* PVA0RDB1 read clients */ 380*4882a593Smuzhiyun #define TEGRA194_MEMORY_CLIENT_PVA0RDB1 0xec 381*4882a593Smuzhiyun /* PVA1RDA1 read clients */ 382*4882a593Smuzhiyun #define TEGRA194_MEMORY_CLIENT_PVA1RDA1 0xed 383*4882a593Smuzhiyun /* PVA1RDB1 read clients */ 384*4882a593Smuzhiyun #define TEGRA194_MEMORY_CLIENT_PVA1RDB1 0xee 385*4882a593Smuzhiyun /* PCIE5r1 read clients */ 386*4882a593Smuzhiyun #define TEGRA194_MEMORY_CLIENT_PCIE5R1 0xef 387*4882a593Smuzhiyun #define TEGRA194_MEMORY_CLIENT_NVENCSRD1 0xf0 388*4882a593Smuzhiyun #define TEGRA194_MEMORY_CLIENT_NVENC1SRD1 0xf1 389*4882a593Smuzhiyun /* ISP read client for Crossbar A */ 390*4882a593Smuzhiyun #define TEGRA194_MEMORY_CLIENT_ISPRA1 0xf2 391*4882a593Smuzhiyun /* PCIE0 read clients */ 392*4882a593Smuzhiyun #define TEGRA194_MEMORY_CLIENT_PCIE0R1 0xf3 393*4882a593Smuzhiyun #define TEGRA194_MEMORY_CLIENT_NVL0RHP 0xf4 394*4882a593Smuzhiyun #define TEGRA194_MEMORY_CLIENT_NVL1RHP 0xf5 395*4882a593Smuzhiyun #define TEGRA194_MEMORY_CLIENT_NVL2RHP 0xf6 396*4882a593Smuzhiyun #define TEGRA194_MEMORY_CLIENT_NVL3RHP 0xf7 397*4882a593Smuzhiyun #define TEGRA194_MEMORY_CLIENT_NVL4RHP 0xf8 398*4882a593Smuzhiyun #define TEGRA194_MEMORY_CLIENT_NVDEC1SRD 0xf9 399*4882a593Smuzhiyun #define TEGRA194_MEMORY_CLIENT_NVDEC1SRD1 0xfa 400*4882a593Smuzhiyun #define TEGRA194_MEMORY_CLIENT_NVDEC1SWR 0xfb 401*4882a593Smuzhiyun /* MSS internal memqual MIU5 read clients */ 402*4882a593Smuzhiyun #define TEGRA194_MEMORY_CLIENT_MIU5R 0xfc 403*4882a593Smuzhiyun /* MSS internal memqual MIU5 write clients */ 404*4882a593Smuzhiyun #define TEGRA194_MEMORY_CLIENT_MIU5W 0xfd 405*4882a593Smuzhiyun /* MSS internal memqual MIU6 read clients */ 406*4882a593Smuzhiyun #define TEGRA194_MEMORY_CLIENT_MIU6R 0xfe 407*4882a593Smuzhiyun /* MSS internal memqual MIU6 write clients */ 408*4882a593Smuzhiyun #define TEGRA194_MEMORY_CLIENT_MIU6W 0xff 409*4882a593Smuzhiyun 410*4882a593Smuzhiyun #endif 411