1*4882a593Smuzhiyun #ifndef DT_BINDINGS_MEMORY_TEGRA186_MC_H 2*4882a593Smuzhiyun #define DT_BINDINGS_MEMORY_TEGRA186_MC_H 3*4882a593Smuzhiyun 4*4882a593Smuzhiyun /* special clients */ 5*4882a593Smuzhiyun #define TEGRA186_SID_INVALID 0x00 6*4882a593Smuzhiyun #define TEGRA186_SID_PASSTHROUGH 0x7f 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun /* host1x clients */ 9*4882a593Smuzhiyun #define TEGRA186_SID_HOST1X 0x01 10*4882a593Smuzhiyun #define TEGRA186_SID_CSI 0x02 11*4882a593Smuzhiyun #define TEGRA186_SID_VIC 0x03 12*4882a593Smuzhiyun #define TEGRA186_SID_VI 0x04 13*4882a593Smuzhiyun #define TEGRA186_SID_ISP 0x05 14*4882a593Smuzhiyun #define TEGRA186_SID_NVDEC 0x06 15*4882a593Smuzhiyun #define TEGRA186_SID_NVENC 0x07 16*4882a593Smuzhiyun #define TEGRA186_SID_NVJPG 0x08 17*4882a593Smuzhiyun #define TEGRA186_SID_NVDISPLAY 0x09 18*4882a593Smuzhiyun #define TEGRA186_SID_TSEC 0x0a 19*4882a593Smuzhiyun #define TEGRA186_SID_TSECB 0x0b 20*4882a593Smuzhiyun #define TEGRA186_SID_SE 0x0c 21*4882a593Smuzhiyun #define TEGRA186_SID_SE1 0x0d 22*4882a593Smuzhiyun #define TEGRA186_SID_SE2 0x0e 23*4882a593Smuzhiyun #define TEGRA186_SID_SE3 0x0f 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun /* GPU clients */ 26*4882a593Smuzhiyun #define TEGRA186_SID_GPU 0x10 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun /* other SoC clients */ 29*4882a593Smuzhiyun #define TEGRA186_SID_AFI 0x11 30*4882a593Smuzhiyun #define TEGRA186_SID_HDA 0x12 31*4882a593Smuzhiyun #define TEGRA186_SID_ETR 0x13 32*4882a593Smuzhiyun #define TEGRA186_SID_EQOS 0x14 33*4882a593Smuzhiyun #define TEGRA186_SID_UFSHC 0x15 34*4882a593Smuzhiyun #define TEGRA186_SID_AON 0x16 35*4882a593Smuzhiyun #define TEGRA186_SID_SDMMC4 0x17 36*4882a593Smuzhiyun #define TEGRA186_SID_SDMMC3 0x18 37*4882a593Smuzhiyun #define TEGRA186_SID_SDMMC2 0x19 38*4882a593Smuzhiyun #define TEGRA186_SID_SDMMC1 0x1a 39*4882a593Smuzhiyun #define TEGRA186_SID_XUSB_HOST 0x1b 40*4882a593Smuzhiyun #define TEGRA186_SID_XUSB_DEV 0x1c 41*4882a593Smuzhiyun #define TEGRA186_SID_SATA 0x1d 42*4882a593Smuzhiyun #define TEGRA186_SID_APE 0x1e 43*4882a593Smuzhiyun #define TEGRA186_SID_SCE 0x1f 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun /* GPC DMA clients */ 46*4882a593Smuzhiyun #define TEGRA186_SID_GPCDMA_0 0x20 47*4882a593Smuzhiyun #define TEGRA186_SID_GPCDMA_1 0x21 48*4882a593Smuzhiyun #define TEGRA186_SID_GPCDMA_2 0x22 49*4882a593Smuzhiyun #define TEGRA186_SID_GPCDMA_3 0x23 50*4882a593Smuzhiyun #define TEGRA186_SID_GPCDMA_4 0x24 51*4882a593Smuzhiyun #define TEGRA186_SID_GPCDMA_5 0x25 52*4882a593Smuzhiyun #define TEGRA186_SID_GPCDMA_6 0x26 53*4882a593Smuzhiyun #define TEGRA186_SID_GPCDMA_7 0x27 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun /* APE DMA clients */ 56*4882a593Smuzhiyun #define TEGRA186_SID_APE_1 0x28 57*4882a593Smuzhiyun #define TEGRA186_SID_APE_2 0x29 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun /* camera RTCPU */ 60*4882a593Smuzhiyun #define TEGRA186_SID_RCE 0x2a 61*4882a593Smuzhiyun 62*4882a593Smuzhiyun /* camera RTCPU on host1x address space */ 63*4882a593Smuzhiyun #define TEGRA186_SID_RCE_1X 0x2b 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun /* APE DMA clients */ 66*4882a593Smuzhiyun #define TEGRA186_SID_APE_3 0x2c 67*4882a593Smuzhiyun 68*4882a593Smuzhiyun /* camera RTCPU running on APE */ 69*4882a593Smuzhiyun #define TEGRA186_SID_APE_CAM 0x2d 70*4882a593Smuzhiyun #define TEGRA186_SID_APE_CAM_1X 0x2e 71*4882a593Smuzhiyun 72*4882a593Smuzhiyun /* 73*4882a593Smuzhiyun * The BPMP has its SID value hardcoded in the firmware. Changing it requires 74*4882a593Smuzhiyun * considerable effort. 75*4882a593Smuzhiyun */ 76*4882a593Smuzhiyun #define TEGRA186_SID_BPMP 0x32 77*4882a593Smuzhiyun 78*4882a593Smuzhiyun /* for SMMU tests */ 79*4882a593Smuzhiyun #define TEGRA186_SID_SMMU_TEST 0x33 80*4882a593Smuzhiyun 81*4882a593Smuzhiyun /* host1x virtualization channels */ 82*4882a593Smuzhiyun #define TEGRA186_SID_HOST1X_CTX0 0x38 83*4882a593Smuzhiyun #define TEGRA186_SID_HOST1X_CTX1 0x39 84*4882a593Smuzhiyun #define TEGRA186_SID_HOST1X_CTX2 0x3a 85*4882a593Smuzhiyun #define TEGRA186_SID_HOST1X_CTX3 0x3b 86*4882a593Smuzhiyun #define TEGRA186_SID_HOST1X_CTX4 0x3c 87*4882a593Smuzhiyun #define TEGRA186_SID_HOST1X_CTX5 0x3d 88*4882a593Smuzhiyun #define TEGRA186_SID_HOST1X_CTX6 0x3e 89*4882a593Smuzhiyun #define TEGRA186_SID_HOST1X_CTX7 0x3f 90*4882a593Smuzhiyun 91*4882a593Smuzhiyun /* host1x command buffers */ 92*4882a593Smuzhiyun #define TEGRA186_SID_HOST1X_VM0 0x40 93*4882a593Smuzhiyun #define TEGRA186_SID_HOST1X_VM1 0x41 94*4882a593Smuzhiyun #define TEGRA186_SID_HOST1X_VM2 0x42 95*4882a593Smuzhiyun #define TEGRA186_SID_HOST1X_VM3 0x43 96*4882a593Smuzhiyun #define TEGRA186_SID_HOST1X_VM4 0x44 97*4882a593Smuzhiyun #define TEGRA186_SID_HOST1X_VM5 0x45 98*4882a593Smuzhiyun #define TEGRA186_SID_HOST1X_VM6 0x46 99*4882a593Smuzhiyun #define TEGRA186_SID_HOST1X_VM7 0x47 100*4882a593Smuzhiyun 101*4882a593Smuzhiyun /* SE data buffers */ 102*4882a593Smuzhiyun #define TEGRA186_SID_SE_VM0 0x48 103*4882a593Smuzhiyun #define TEGRA186_SID_SE_VM1 0x49 104*4882a593Smuzhiyun #define TEGRA186_SID_SE_VM2 0x4a 105*4882a593Smuzhiyun #define TEGRA186_SID_SE_VM3 0x4b 106*4882a593Smuzhiyun #define TEGRA186_SID_SE_VM4 0x4c 107*4882a593Smuzhiyun #define TEGRA186_SID_SE_VM5 0x4d 108*4882a593Smuzhiyun #define TEGRA186_SID_SE_VM6 0x4e 109*4882a593Smuzhiyun #define TEGRA186_SID_SE_VM7 0x4f 110*4882a593Smuzhiyun 111*4882a593Smuzhiyun /* 112*4882a593Smuzhiyun * memory client IDs 113*4882a593Smuzhiyun */ 114*4882a593Smuzhiyun 115*4882a593Smuzhiyun /* Misses from System Memory Management Unit (SMMU) Page Table Cache (PTC) */ 116*4882a593Smuzhiyun #define TEGRA186_MEMORY_CLIENT_PTCR 0x00 117*4882a593Smuzhiyun /* PCIE reads */ 118*4882a593Smuzhiyun #define TEGRA186_MEMORY_CLIENT_AFIR 0x0e 119*4882a593Smuzhiyun /* High-definition audio (HDA) reads */ 120*4882a593Smuzhiyun #define TEGRA186_MEMORY_CLIENT_HDAR 0x15 121*4882a593Smuzhiyun /* Host channel data reads */ 122*4882a593Smuzhiyun #define TEGRA186_MEMORY_CLIENT_HOST1XDMAR 0x16 123*4882a593Smuzhiyun #define TEGRA186_MEMORY_CLIENT_NVENCSRD 0x1c 124*4882a593Smuzhiyun /* SATA reads */ 125*4882a593Smuzhiyun #define TEGRA186_MEMORY_CLIENT_SATAR 0x1f 126*4882a593Smuzhiyun /* Reads from Cortex-A9 4 CPU cores via the L2 cache */ 127*4882a593Smuzhiyun #define TEGRA186_MEMORY_CLIENT_MPCORER 0x27 128*4882a593Smuzhiyun #define TEGRA186_MEMORY_CLIENT_NVENCSWR 0x2b 129*4882a593Smuzhiyun /* PCIE writes */ 130*4882a593Smuzhiyun #define TEGRA186_MEMORY_CLIENT_AFIW 0x31 131*4882a593Smuzhiyun /* High-definition audio (HDA) writes */ 132*4882a593Smuzhiyun #define TEGRA186_MEMORY_CLIENT_HDAW 0x35 133*4882a593Smuzhiyun /* Writes from Cortex-A9 4 CPU cores via the L2 cache */ 134*4882a593Smuzhiyun #define TEGRA186_MEMORY_CLIENT_MPCOREW 0x39 135*4882a593Smuzhiyun /* SATA writes */ 136*4882a593Smuzhiyun #define TEGRA186_MEMORY_CLIENT_SATAW 0x3d 137*4882a593Smuzhiyun /* ISP Read client for Crossbar A */ 138*4882a593Smuzhiyun #define TEGRA186_MEMORY_CLIENT_ISPRA 0x44 139*4882a593Smuzhiyun /* ISP Write client for Crossbar A */ 140*4882a593Smuzhiyun #define TEGRA186_MEMORY_CLIENT_ISPWA 0x46 141*4882a593Smuzhiyun /* ISP Write client Crossbar B */ 142*4882a593Smuzhiyun #define TEGRA186_MEMORY_CLIENT_ISPWB 0x47 143*4882a593Smuzhiyun /* XUSB reads */ 144*4882a593Smuzhiyun #define TEGRA186_MEMORY_CLIENT_XUSB_HOSTR 0x4a 145*4882a593Smuzhiyun /* XUSB_HOST writes */ 146*4882a593Smuzhiyun #define TEGRA186_MEMORY_CLIENT_XUSB_HOSTW 0x4b 147*4882a593Smuzhiyun /* XUSB reads */ 148*4882a593Smuzhiyun #define TEGRA186_MEMORY_CLIENT_XUSB_DEVR 0x4c 149*4882a593Smuzhiyun /* XUSB_DEV writes */ 150*4882a593Smuzhiyun #define TEGRA186_MEMORY_CLIENT_XUSB_DEVW 0x4d 151*4882a593Smuzhiyun /* TSEC Memory Return Data Client Description */ 152*4882a593Smuzhiyun #define TEGRA186_MEMORY_CLIENT_TSECSRD 0x54 153*4882a593Smuzhiyun /* TSEC Memory Write Client Description */ 154*4882a593Smuzhiyun #define TEGRA186_MEMORY_CLIENT_TSECSWR 0x55 155*4882a593Smuzhiyun /* 3D, ltcx reads instance 0 */ 156*4882a593Smuzhiyun #define TEGRA186_MEMORY_CLIENT_GPUSRD 0x58 157*4882a593Smuzhiyun /* 3D, ltcx writes instance 0 */ 158*4882a593Smuzhiyun #define TEGRA186_MEMORY_CLIENT_GPUSWR 0x59 159*4882a593Smuzhiyun /* sdmmca memory read client */ 160*4882a593Smuzhiyun #define TEGRA186_MEMORY_CLIENT_SDMMCRA 0x60 161*4882a593Smuzhiyun /* sdmmcbmemory read client */ 162*4882a593Smuzhiyun #define TEGRA186_MEMORY_CLIENT_SDMMCRAA 0x61 163*4882a593Smuzhiyun /* sdmmc memory read client */ 164*4882a593Smuzhiyun #define TEGRA186_MEMORY_CLIENT_SDMMCR 0x62 165*4882a593Smuzhiyun /* sdmmcd memory read client */ 166*4882a593Smuzhiyun #define TEGRA186_MEMORY_CLIENT_SDMMCRAB 0x63 167*4882a593Smuzhiyun /* sdmmca memory write client */ 168*4882a593Smuzhiyun #define TEGRA186_MEMORY_CLIENT_SDMMCWA 0x64 169*4882a593Smuzhiyun /* sdmmcb memory write client */ 170*4882a593Smuzhiyun #define TEGRA186_MEMORY_CLIENT_SDMMCWAA 0x65 171*4882a593Smuzhiyun /* sdmmc memory write client */ 172*4882a593Smuzhiyun #define TEGRA186_MEMORY_CLIENT_SDMMCW 0x66 173*4882a593Smuzhiyun /* sdmmcd memory write client */ 174*4882a593Smuzhiyun #define TEGRA186_MEMORY_CLIENT_SDMMCWAB 0x67 175*4882a593Smuzhiyun #define TEGRA186_MEMORY_CLIENT_VICSRD 0x6c 176*4882a593Smuzhiyun #define TEGRA186_MEMORY_CLIENT_VICSWR 0x6d 177*4882a593Smuzhiyun /* VI Write client */ 178*4882a593Smuzhiyun #define TEGRA186_MEMORY_CLIENT_VIW 0x72 179*4882a593Smuzhiyun #define TEGRA186_MEMORY_CLIENT_NVDECSRD 0x78 180*4882a593Smuzhiyun #define TEGRA186_MEMORY_CLIENT_NVDECSWR 0x79 181*4882a593Smuzhiyun /* Audio Processing (APE) engine reads */ 182*4882a593Smuzhiyun #define TEGRA186_MEMORY_CLIENT_APER 0x7a 183*4882a593Smuzhiyun /* Audio Processing (APE) engine writes */ 184*4882a593Smuzhiyun #define TEGRA186_MEMORY_CLIENT_APEW 0x7b 185*4882a593Smuzhiyun #define TEGRA186_MEMORY_CLIENT_NVJPGSRD 0x7e 186*4882a593Smuzhiyun #define TEGRA186_MEMORY_CLIENT_NVJPGSWR 0x7f 187*4882a593Smuzhiyun /* SE Memory Return Data Client Description */ 188*4882a593Smuzhiyun #define TEGRA186_MEMORY_CLIENT_SESRD 0x80 189*4882a593Smuzhiyun /* SE Memory Write Client Description */ 190*4882a593Smuzhiyun #define TEGRA186_MEMORY_CLIENT_SESWR 0x81 191*4882a593Smuzhiyun /* ETR reads */ 192*4882a593Smuzhiyun #define TEGRA186_MEMORY_CLIENT_ETRR 0x84 193*4882a593Smuzhiyun /* ETR writes */ 194*4882a593Smuzhiyun #define TEGRA186_MEMORY_CLIENT_ETRW 0x85 195*4882a593Smuzhiyun /* TSECB Memory Return Data Client Description */ 196*4882a593Smuzhiyun #define TEGRA186_MEMORY_CLIENT_TSECSRDB 0x86 197*4882a593Smuzhiyun /* TSECB Memory Write Client Description */ 198*4882a593Smuzhiyun #define TEGRA186_MEMORY_CLIENT_TSECSWRB 0x87 199*4882a593Smuzhiyun /* 3D, ltcx reads instance 1 */ 200*4882a593Smuzhiyun #define TEGRA186_MEMORY_CLIENT_GPUSRD2 0x88 201*4882a593Smuzhiyun /* 3D, ltcx writes instance 1 */ 202*4882a593Smuzhiyun #define TEGRA186_MEMORY_CLIENT_GPUSWR2 0x89 203*4882a593Smuzhiyun /* AXI Switch read client */ 204*4882a593Smuzhiyun #define TEGRA186_MEMORY_CLIENT_AXISR 0x8c 205*4882a593Smuzhiyun /* AXI Switch write client */ 206*4882a593Smuzhiyun #define TEGRA186_MEMORY_CLIENT_AXISW 0x8d 207*4882a593Smuzhiyun /* EQOS read client */ 208*4882a593Smuzhiyun #define TEGRA186_MEMORY_CLIENT_EQOSR 0x8e 209*4882a593Smuzhiyun /* EQOS write client */ 210*4882a593Smuzhiyun #define TEGRA186_MEMORY_CLIENT_EQOSW 0x8f 211*4882a593Smuzhiyun /* UFSHC read client */ 212*4882a593Smuzhiyun #define TEGRA186_MEMORY_CLIENT_UFSHCR 0x90 213*4882a593Smuzhiyun /* UFSHC write client */ 214*4882a593Smuzhiyun #define TEGRA186_MEMORY_CLIENT_UFSHCW 0x91 215*4882a593Smuzhiyun /* NVDISPLAY read client */ 216*4882a593Smuzhiyun #define TEGRA186_MEMORY_CLIENT_NVDISPLAYR 0x92 217*4882a593Smuzhiyun /* BPMP read client */ 218*4882a593Smuzhiyun #define TEGRA186_MEMORY_CLIENT_BPMPR 0x93 219*4882a593Smuzhiyun /* BPMP write client */ 220*4882a593Smuzhiyun #define TEGRA186_MEMORY_CLIENT_BPMPW 0x94 221*4882a593Smuzhiyun /* BPMPDMA read client */ 222*4882a593Smuzhiyun #define TEGRA186_MEMORY_CLIENT_BPMPDMAR 0x95 223*4882a593Smuzhiyun /* BPMPDMA write client */ 224*4882a593Smuzhiyun #define TEGRA186_MEMORY_CLIENT_BPMPDMAW 0x96 225*4882a593Smuzhiyun /* AON read client */ 226*4882a593Smuzhiyun #define TEGRA186_MEMORY_CLIENT_AONR 0x97 227*4882a593Smuzhiyun /* AON write client */ 228*4882a593Smuzhiyun #define TEGRA186_MEMORY_CLIENT_AONW 0x98 229*4882a593Smuzhiyun /* AONDMA read client */ 230*4882a593Smuzhiyun #define TEGRA186_MEMORY_CLIENT_AONDMAR 0x99 231*4882a593Smuzhiyun /* AONDMA write client */ 232*4882a593Smuzhiyun #define TEGRA186_MEMORY_CLIENT_AONDMAW 0x9a 233*4882a593Smuzhiyun /* SCE read client */ 234*4882a593Smuzhiyun #define TEGRA186_MEMORY_CLIENT_SCER 0x9b 235*4882a593Smuzhiyun /* SCE write client */ 236*4882a593Smuzhiyun #define TEGRA186_MEMORY_CLIENT_SCEW 0x9c 237*4882a593Smuzhiyun /* SCEDMA read client */ 238*4882a593Smuzhiyun #define TEGRA186_MEMORY_CLIENT_SCEDMAR 0x9d 239*4882a593Smuzhiyun /* SCEDMA write client */ 240*4882a593Smuzhiyun #define TEGRA186_MEMORY_CLIENT_SCEDMAW 0x9e 241*4882a593Smuzhiyun /* APEDMA read client */ 242*4882a593Smuzhiyun #define TEGRA186_MEMORY_CLIENT_APEDMAR 0x9f 243*4882a593Smuzhiyun /* APEDMA write client */ 244*4882a593Smuzhiyun #define TEGRA186_MEMORY_CLIENT_APEDMAW 0xa0 245*4882a593Smuzhiyun /* NVDISPLAY read client instance 2 */ 246*4882a593Smuzhiyun #define TEGRA186_MEMORY_CLIENT_NVDISPLAYR1 0xa1 247*4882a593Smuzhiyun #define TEGRA186_MEMORY_CLIENT_VICSRD1 0xa2 248*4882a593Smuzhiyun #define TEGRA186_MEMORY_CLIENT_NVDECSRD1 0xa3 249*4882a593Smuzhiyun 250*4882a593Smuzhiyun #endif 251