1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun #ifndef DT_BINDINGS_MEMORY_TEGRA124_MC_H 3*4882a593Smuzhiyun #define DT_BINDINGS_MEMORY_TEGRA124_MC_H 4*4882a593Smuzhiyun 5*4882a593Smuzhiyun #define TEGRA_SWGROUP_PTC 0 6*4882a593Smuzhiyun #define TEGRA_SWGROUP_DC 1 7*4882a593Smuzhiyun #define TEGRA_SWGROUP_DCB 2 8*4882a593Smuzhiyun #define TEGRA_SWGROUP_AFI 3 9*4882a593Smuzhiyun #define TEGRA_SWGROUP_AVPC 4 10*4882a593Smuzhiyun #define TEGRA_SWGROUP_HDA 5 11*4882a593Smuzhiyun #define TEGRA_SWGROUP_HC 6 12*4882a593Smuzhiyun #define TEGRA_SWGROUP_MSENC 7 13*4882a593Smuzhiyun #define TEGRA_SWGROUP_PPCS 8 14*4882a593Smuzhiyun #define TEGRA_SWGROUP_SATA 9 15*4882a593Smuzhiyun #define TEGRA_SWGROUP_VDE 10 16*4882a593Smuzhiyun #define TEGRA_SWGROUP_MPCORELP 11 17*4882a593Smuzhiyun #define TEGRA_SWGROUP_MPCORE 12 18*4882a593Smuzhiyun #define TEGRA_SWGROUP_ISP2 13 19*4882a593Smuzhiyun #define TEGRA_SWGROUP_XUSB_HOST 14 20*4882a593Smuzhiyun #define TEGRA_SWGROUP_XUSB_DEV 15 21*4882a593Smuzhiyun #define TEGRA_SWGROUP_ISP2B 16 22*4882a593Smuzhiyun #define TEGRA_SWGROUP_TSEC 17 23*4882a593Smuzhiyun #define TEGRA_SWGROUP_A9AVP 18 24*4882a593Smuzhiyun #define TEGRA_SWGROUP_GPU 19 25*4882a593Smuzhiyun #define TEGRA_SWGROUP_SDMMC1A 20 26*4882a593Smuzhiyun #define TEGRA_SWGROUP_SDMMC2A 21 27*4882a593Smuzhiyun #define TEGRA_SWGROUP_SDMMC3A 22 28*4882a593Smuzhiyun #define TEGRA_SWGROUP_SDMMC4A 23 29*4882a593Smuzhiyun #define TEGRA_SWGROUP_VIC 24 30*4882a593Smuzhiyun #define TEGRA_SWGROUP_VI 25 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun #define TEGRA124_MC_RESET_AFI 0 33*4882a593Smuzhiyun #define TEGRA124_MC_RESET_AVPC 1 34*4882a593Smuzhiyun #define TEGRA124_MC_RESET_DC 2 35*4882a593Smuzhiyun #define TEGRA124_MC_RESET_DCB 3 36*4882a593Smuzhiyun #define TEGRA124_MC_RESET_HC 4 37*4882a593Smuzhiyun #define TEGRA124_MC_RESET_HDA 5 38*4882a593Smuzhiyun #define TEGRA124_MC_RESET_ISP2 6 39*4882a593Smuzhiyun #define TEGRA124_MC_RESET_MPCORE 7 40*4882a593Smuzhiyun #define TEGRA124_MC_RESET_MPCORELP 8 41*4882a593Smuzhiyun #define TEGRA124_MC_RESET_MSENC 9 42*4882a593Smuzhiyun #define TEGRA124_MC_RESET_PPCS 10 43*4882a593Smuzhiyun #define TEGRA124_MC_RESET_SATA 11 44*4882a593Smuzhiyun #define TEGRA124_MC_RESET_VDE 12 45*4882a593Smuzhiyun #define TEGRA124_MC_RESET_VI 13 46*4882a593Smuzhiyun #define TEGRA124_MC_RESET_VIC 14 47*4882a593Smuzhiyun #define TEGRA124_MC_RESET_XUSB_HOST 15 48*4882a593Smuzhiyun #define TEGRA124_MC_RESET_XUSB_DEV 16 49*4882a593Smuzhiyun #define TEGRA124_MC_RESET_TSEC 17 50*4882a593Smuzhiyun #define TEGRA124_MC_RESET_SDMMC1 18 51*4882a593Smuzhiyun #define TEGRA124_MC_RESET_SDMMC2 19 52*4882a593Smuzhiyun #define TEGRA124_MC_RESET_SDMMC3 20 53*4882a593Smuzhiyun #define TEGRA124_MC_RESET_SDMMC4 21 54*4882a593Smuzhiyun #define TEGRA124_MC_RESET_ISP2B 22 55*4882a593Smuzhiyun #define TEGRA124_MC_RESET_GPU 23 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun #endif 58