1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun #ifndef DT_BINDINGS_MEMORY_TEGRA114_MC_H 3*4882a593Smuzhiyun #define DT_BINDINGS_MEMORY_TEGRA114_MC_H 4*4882a593Smuzhiyun 5*4882a593Smuzhiyun #define TEGRA_SWGROUP_PTC 0 6*4882a593Smuzhiyun #define TEGRA_SWGROUP_DC 1 7*4882a593Smuzhiyun #define TEGRA_SWGROUP_DCB 2 8*4882a593Smuzhiyun #define TEGRA_SWGROUP_EPP 3 9*4882a593Smuzhiyun #define TEGRA_SWGROUP_G2 4 10*4882a593Smuzhiyun #define TEGRA_SWGROUP_AVPC 5 11*4882a593Smuzhiyun #define TEGRA_SWGROUP_NV 6 12*4882a593Smuzhiyun #define TEGRA_SWGROUP_HDA 7 13*4882a593Smuzhiyun #define TEGRA_SWGROUP_HC 8 14*4882a593Smuzhiyun #define TEGRA_SWGROUP_MSENC 9 15*4882a593Smuzhiyun #define TEGRA_SWGROUP_PPCS 10 16*4882a593Smuzhiyun #define TEGRA_SWGROUP_VDE 11 17*4882a593Smuzhiyun #define TEGRA_SWGROUP_MPCORELP 12 18*4882a593Smuzhiyun #define TEGRA_SWGROUP_MPCORE 13 19*4882a593Smuzhiyun #define TEGRA_SWGROUP_VI 14 20*4882a593Smuzhiyun #define TEGRA_SWGROUP_ISP 15 21*4882a593Smuzhiyun #define TEGRA_SWGROUP_XUSB_HOST 16 22*4882a593Smuzhiyun #define TEGRA_SWGROUP_XUSB_DEV 17 23*4882a593Smuzhiyun #define TEGRA_SWGROUP_EMUCIF 18 24*4882a593Smuzhiyun #define TEGRA_SWGROUP_TSEC 19 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun #define TEGRA114_MC_RESET_AVPC 0 27*4882a593Smuzhiyun #define TEGRA114_MC_RESET_DC 1 28*4882a593Smuzhiyun #define TEGRA114_MC_RESET_DCB 2 29*4882a593Smuzhiyun #define TEGRA114_MC_RESET_EPP 3 30*4882a593Smuzhiyun #define TEGRA114_MC_RESET_2D 4 31*4882a593Smuzhiyun #define TEGRA114_MC_RESET_HC 5 32*4882a593Smuzhiyun #define TEGRA114_MC_RESET_HDA 6 33*4882a593Smuzhiyun #define TEGRA114_MC_RESET_ISP 7 34*4882a593Smuzhiyun #define TEGRA114_MC_RESET_MPCORE 8 35*4882a593Smuzhiyun #define TEGRA114_MC_RESET_MPCORELP 9 36*4882a593Smuzhiyun #define TEGRA114_MC_RESET_MPE 10 37*4882a593Smuzhiyun #define TEGRA114_MC_RESET_3D 11 38*4882a593Smuzhiyun #define TEGRA114_MC_RESET_3D2 12 39*4882a593Smuzhiyun #define TEGRA114_MC_RESET_PPCS 13 40*4882a593Smuzhiyun #define TEGRA114_MC_RESET_VDE 14 41*4882a593Smuzhiyun #define TEGRA114_MC_RESET_VI 15 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun #endif 44