1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * This file is dual-licensed: you can use it either under the terms 5*4882a593Smuzhiyun * of the GPL or the X11 license, at your option. Note that this dual 6*4882a593Smuzhiyun * licensing only applies to this file, and not this project as a 7*4882a593Smuzhiyun * whole. 8*4882a593Smuzhiyun * 9*4882a593Smuzhiyun * a) This library is free software; you can redistribute it and/or 10*4882a593Smuzhiyun * modify it under the terms of the GNU General Public License as 11*4882a593Smuzhiyun * published by the Free Software Foundation; either version 2 of the 12*4882a593Smuzhiyun * License, or (at your option) any later version. 13*4882a593Smuzhiyun * 14*4882a593Smuzhiyun * This library is distributed in the hope that it will be useful, 15*4882a593Smuzhiyun * but WITHOUT ANY WARRANTY; without even the implied warranty of 16*4882a593Smuzhiyun * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17*4882a593Smuzhiyun * GNU General Public License for more details. 18*4882a593Smuzhiyun * 19*4882a593Smuzhiyun * Or, alternatively, 20*4882a593Smuzhiyun * 21*4882a593Smuzhiyun * b) Permission is hereby granted, free of charge, to any person 22*4882a593Smuzhiyun * obtaining a copy of this software and associated documentation 23*4882a593Smuzhiyun * files (the "Software"), to deal in the Software without 24*4882a593Smuzhiyun * restriction, including without limitation the rights to use, 25*4882a593Smuzhiyun * copy, modify, merge, publish, distribute, sublicense, and/or 26*4882a593Smuzhiyun * sell copies of the Software, and to permit persons to whom the 27*4882a593Smuzhiyun * Software is furnished to do so, subject to the following 28*4882a593Smuzhiyun * conditions: 29*4882a593Smuzhiyun * 30*4882a593Smuzhiyun * The above copyright notice and this permission notice shall be 31*4882a593Smuzhiyun * included in all copies or substantial portions of the Software. 32*4882a593Smuzhiyun * 33*4882a593Smuzhiyun * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 34*4882a593Smuzhiyun * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 35*4882a593Smuzhiyun * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 36*4882a593Smuzhiyun * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 37*4882a593Smuzhiyun * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 38*4882a593Smuzhiyun * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 39*4882a593Smuzhiyun * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 40*4882a593Smuzhiyun * OTHER DEALINGS IN THE SOFTWARE. 41*4882a593Smuzhiyun */ 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun #ifndef _DT_BINDINGS_DRAM_ROCKCHIP_RK3128_H 44*4882a593Smuzhiyun #define _DT_BINDINGS_DRAM_ROCKCHIP_RK3128_H 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun #define BIT(nr) (1UL << (nr)) 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun #define DDR3_DS_34ohm BIT(1) 49*4882a593Smuzhiyun #define DDR3_DS_40ohm (0x0) 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun #define LP2_DS_34ohm (0x1) 52*4882a593Smuzhiyun #define LP2_DS_40ohm (0x2) 53*4882a593Smuzhiyun #define LP2_DS_48ohm (0x3) 54*4882a593Smuzhiyun #define LP2_DS_60ohm (0x4) 55*4882a593Smuzhiyun #define LP2_DS_68_6ohm (0x5) /* optional */ 56*4882a593Smuzhiyun #define LP2_DS_80ohm (0x6) 57*4882a593Smuzhiyun #define LP2_DS_120ohm (0x7) /* optional */ 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun #define DDR3_ODT_DIS (0) 60*4882a593Smuzhiyun #define DDR3_ODT_40ohm (BIT(2) | BIT(6)) 61*4882a593Smuzhiyun #define DDR3_ODT_60ohm BIT(2) 62*4882a593Smuzhiyun #define DDR3_ODT_120ohm BIT(6) 63*4882a593Smuzhiyun 64*4882a593Smuzhiyun #define PHY_RON_DISABLE (0) 65*4882a593Smuzhiyun #define PHY_RON_309ohm (1) 66*4882a593Smuzhiyun #define PHY_RON_155ohm (2) 67*4882a593Smuzhiyun #define PHY_RON_103ohm (3) 68*4882a593Smuzhiyun #define PHY_RON_77ohm (4) 69*4882a593Smuzhiyun #define PHY_RON_63ohm (5) 70*4882a593Smuzhiyun #define PHY_RON_52ohm (6) 71*4882a593Smuzhiyun #define PHY_RON_45ohm (7) 72*4882a593Smuzhiyun #define PHY_RON_62ohm (9) 73*4882a593Smuzhiyun #define PHY_RON_44ohm (11) 74*4882a593Smuzhiyun #define PHY_RON_39ohm (12) 75*4882a593Smuzhiyun #define PHY_RON_34ohm (13) 76*4882a593Smuzhiyun #define PHY_RON_31ohm (14) 77*4882a593Smuzhiyun #define PHY_RON_28ohm (15) 78*4882a593Smuzhiyun 79*4882a593Smuzhiyun #define PHY_RTT_DISABLE (0) 80*4882a593Smuzhiyun #define PHY_RTT_816ohm (1) 81*4882a593Smuzhiyun #define PHY_RTT_431ohm (2) 82*4882a593Smuzhiyun #define PHY_RTT_287ohm (3) 83*4882a593Smuzhiyun #define PHY_RTT_216ohm (4) 84*4882a593Smuzhiyun #define PHY_RTT_172ohm (5) 85*4882a593Smuzhiyun #define PHY_RTT_145ohm (6) 86*4882a593Smuzhiyun #define PHY_RTT_124ohm (7) 87*4882a593Smuzhiyun #define PHY_RTT_215ohm (8) 88*4882a593Smuzhiyun #define PHY_RTT_144ohm (10) 89*4882a593Smuzhiyun #define PHY_RTT_123ohm (11) 90*4882a593Smuzhiyun #define PHY_RTT_108ohm (12) 91*4882a593Smuzhiyun #define PHY_RTT_96ohm (13) 92*4882a593Smuzhiyun #define PHY_RTT_86ohm (14) 93*4882a593Smuzhiyun #define PHY_RTT_78ohm (15) 94*4882a593Smuzhiyun 95*4882a593Smuzhiyun #endif /* _DT_BINDINGS_DRAM_ROCKCHIP_RK3128_H */ 96