1*4882a593Smuzhiyun /* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun #ifndef _DT_BINDINGS_DRAM_ROCKCHIP_RK1808_H 7*4882a593Smuzhiyun #define _DT_BINDINGS_DRAM_ROCKCHIP_RK1808_H 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #define DDR2_DS_FULL (0) 10*4882a593Smuzhiyun #define DDR2_DS_REDUCE (1) 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #define DDR2_ODT_DIS (0) 13*4882a593Smuzhiyun #define DDR2_ODT_50ohm (50) /* optional */ 14*4882a593Smuzhiyun #define DDR2_ODT_75ohm (75) 15*4882a593Smuzhiyun #define DDR2_ODT_150ohm (150) 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun #define DDR3_DS_34ohm (34) 18*4882a593Smuzhiyun #define DDR3_DS_40ohm (40) 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun #define DDR3_ODT_DIS (0) 21*4882a593Smuzhiyun #define DDR3_ODT_40ohm (40) 22*4882a593Smuzhiyun #define DDR3_ODT_60ohm (60) 23*4882a593Smuzhiyun #define DDR3_ODT_120ohm (120) 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun #define LP2_DS_34ohm (34) 26*4882a593Smuzhiyun #define LP2_DS_40ohm (40) 27*4882a593Smuzhiyun #define LP2_DS_48ohm (48) 28*4882a593Smuzhiyun #define LP2_DS_60ohm (60) 29*4882a593Smuzhiyun #define LP2_DS_68_6ohm (68) /* optional */ 30*4882a593Smuzhiyun #define LP2_DS_80ohm (80) 31*4882a593Smuzhiyun #define LP2_DS_120ohm (120) /* optional */ 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun #define LP3_DS_34ohm (34) 34*4882a593Smuzhiyun #define LP3_DS_40ohm (40) 35*4882a593Smuzhiyun #define LP3_DS_48ohm (48) 36*4882a593Smuzhiyun #define LP3_DS_60ohm (60) 37*4882a593Smuzhiyun #define LP3_DS_80ohm (80) 38*4882a593Smuzhiyun #define LP3_DS_34D_40U (3440) 39*4882a593Smuzhiyun #define LP3_DS_40D_48U (4048) 40*4882a593Smuzhiyun #define LP3_DS_34D_48U (3448) 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun #define LP3_ODT_DIS (0) 43*4882a593Smuzhiyun #define LP3_ODT_60ohm (60) 44*4882a593Smuzhiyun #define LP3_ODT_120ohm (120) 45*4882a593Smuzhiyun #define LP3_ODT_240ohm (240) 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun #define LP4_PDDS_40ohm (40) 48*4882a593Smuzhiyun #define LP4_PDDS_48ohm (48) 49*4882a593Smuzhiyun #define LP4_PDDS_60ohm (60) 50*4882a593Smuzhiyun #define LP4_PDDS_80ohm (80) 51*4882a593Smuzhiyun #define LP4_PDDS_120ohm (120) 52*4882a593Smuzhiyun #define LP4_PDDS_240ohm (240) 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun #define LP4_DQ_ODT_40ohm (40) 55*4882a593Smuzhiyun #define LP4_DQ_ODT_48ohm (48) 56*4882a593Smuzhiyun #define LP4_DQ_ODT_60ohm (60) 57*4882a593Smuzhiyun #define LP4_DQ_ODT_80ohm (80) 58*4882a593Smuzhiyun #define LP4_DQ_ODT_120ohm (120) 59*4882a593Smuzhiyun #define LP4_DQ_ODT_240ohm (240) 60*4882a593Smuzhiyun #define LP4_DQ_ODT_DIS (0) 61*4882a593Smuzhiyun 62*4882a593Smuzhiyun #define LP4_CA_ODT_40ohm (40) 63*4882a593Smuzhiyun #define LP4_CA_ODT_48ohm (48) 64*4882a593Smuzhiyun #define LP4_CA_ODT_60ohm (60) 65*4882a593Smuzhiyun #define LP4_CA_ODT_80ohm (80) 66*4882a593Smuzhiyun #define LP4_CA_ODT_120ohm (120) 67*4882a593Smuzhiyun #define LP4_CA_ODT_240ohm (240) 68*4882a593Smuzhiyun #define LP4_CA_ODT_DIS (0) 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun #define DDR4_DS_34ohm (34) 71*4882a593Smuzhiyun #define DDR4_DS_48ohm (48) 72*4882a593Smuzhiyun #define DDR4_RTT_NOM_DIS (0) 73*4882a593Smuzhiyun #define DDR4_RTT_NOM_60ohm (60) 74*4882a593Smuzhiyun #define DDR4_RTT_NOM_120ohm (120) 75*4882a593Smuzhiyun #define DDR4_RTT_NOM_40ohm (40) 76*4882a593Smuzhiyun #define DDR4_RTT_NOM_240ohm (240) 77*4882a593Smuzhiyun #define DDR4_RTT_NOM_48ohm (48) 78*4882a593Smuzhiyun #define DDR4_RTT_NOM_80ohm (80) 79*4882a593Smuzhiyun #define DDR4_RTT_NOM_34ohm (34) 80*4882a593Smuzhiyun 81*4882a593Smuzhiyun #define PHY_DDR3_RON_DISABLE (0) 82*4882a593Smuzhiyun #define PHY_DDR3_RON_340ohm (1) 83*4882a593Smuzhiyun #define PHY_DDR3_RON_170ohm (2) 84*4882a593Smuzhiyun #define PHY_DDR3_RON_113ohm (3) 85*4882a593Smuzhiyun #define PHY_DDR3_RON_85ohm (4) 86*4882a593Smuzhiyun #define PHY_DDR3_RON_68ohm (5) 87*4882a593Smuzhiyun #define PHY_DDR3_RON_57ohm (6) 88*4882a593Smuzhiyun #define PHY_DDR3_RON_49ohm (7) 89*4882a593Smuzhiyun #define PHY_DDR3_RON_43ohm (16) 90*4882a593Smuzhiyun #define PHY_DDR3_RON_38ohm (17) 91*4882a593Smuzhiyun #define PHY_DDR3_RON_34ohm (18) 92*4882a593Smuzhiyun #define PHY_DDR3_RON_31ohm (19) 93*4882a593Smuzhiyun #define PHY_DDR3_RON_28ohm (20) 94*4882a593Smuzhiyun #define PHY_DDR3_RON_26ohm (21) 95*4882a593Smuzhiyun #define PHY_DDR3_RON_24ohm (22) 96*4882a593Smuzhiyun #define PHY_DDR3_RON_23ohm (23) 97*4882a593Smuzhiyun #define PHY_DDR3_RON_21ohm (24) 98*4882a593Smuzhiyun #define PHY_DDR3_RON_20ohm (25) 99*4882a593Smuzhiyun #define PHY_DDR3_RON_19ohm (26) 100*4882a593Smuzhiyun #define PHY_DDR3_RON_18ohm (27) 101*4882a593Smuzhiyun #define PHY_DDR3_RON_17ohm (28) 102*4882a593Smuzhiyun #define PHY_DDR3_RON_16ohm (29) 103*4882a593Smuzhiyun #define PHY_DDR3_RON_15ohm (31) 104*4882a593Smuzhiyun 105*4882a593Smuzhiyun #define PHY_DDR3_RTT_DISABLE (0) 106*4882a593Smuzhiyun #define PHY_DDR3_RTT_852ohm (1) 107*4882a593Smuzhiyun #define PHY_DDR3_RTT_427ohm (2) 108*4882a593Smuzhiyun #define PHY_DDR3_RTT_284ohm (3) 109*4882a593Smuzhiyun #define PHY_DDR3_RTT_213ohm (4) 110*4882a593Smuzhiyun #define PHY_DDR3_RTT_171ohm (5) 111*4882a593Smuzhiyun #define PHY_DDR3_RTT_142ohm (6) 112*4882a593Smuzhiyun #define PHY_DDR3_RTT_122ohm (7) 113*4882a593Smuzhiyun #define PHY_DDR3_RTT_107ohm (16) 114*4882a593Smuzhiyun #define PHY_DDR3_RTT_95ohm (17) 115*4882a593Smuzhiyun #define PHY_DDR3_RTT_85ohm (18) 116*4882a593Smuzhiyun #define PHY_DDR3_RTT_78ohm (19) 117*4882a593Smuzhiyun #define PHY_DDR3_RTT_71ohm (20) 118*4882a593Smuzhiyun #define PHY_DDR3_RTT_66ohm (21) 119*4882a593Smuzhiyun #define PHY_DDR3_RTT_61ohm (22) 120*4882a593Smuzhiyun #define PHY_DDR3_RTT_57ohm (23) 121*4882a593Smuzhiyun #define PHY_DDR3_RTT_53ohm (24) 122*4882a593Smuzhiyun #define PHY_DDR3_RTT_50ohm (25) 123*4882a593Smuzhiyun #define PHY_DDR3_RTT_47ohm (26) 124*4882a593Smuzhiyun #define PHY_DDR3_RTT_45ohm (27) 125*4882a593Smuzhiyun #define PHY_DDR3_RTT_43ohm (28) 126*4882a593Smuzhiyun #define PHY_DDR3_RTT_41ohm (29) 127*4882a593Smuzhiyun #define PHY_DDR3_RTT_39ohm (30) 128*4882a593Smuzhiyun #define PHY_DDR3_RTT_37ohm (31) 129*4882a593Smuzhiyun 130*4882a593Smuzhiyun #define PHY_DDR4_LPDDR2_3_RON_DISABLE (0) 131*4882a593Smuzhiyun #define PHY_DDR4_LPDDR2_3_RON_376ohm (1) 132*4882a593Smuzhiyun #define PHY_DDR4_LPDDR2_3_RON_188ohm (2) 133*4882a593Smuzhiyun #define PHY_DDR4_LPDDR2_3_RON_125ohm (3) 134*4882a593Smuzhiyun #define PHY_DDR4_LPDDR2_3_RON_94ohm (4) 135*4882a593Smuzhiyun #define PHY_DDR4_LPDDR2_3_RON_75ohm (5) 136*4882a593Smuzhiyun #define PHY_DDR4_LPDDR2_3_RON_63ohm (6) 137*4882a593Smuzhiyun #define PHY_DDR4_LPDDR2_3_RON_54ohm (7) 138*4882a593Smuzhiyun #define PHY_DDR4_LPDDR2_3_RON_47ohm (16) 139*4882a593Smuzhiyun #define PHY_DDR4_LPDDR2_3_RON_42ohm (17) 140*4882a593Smuzhiyun #define PHY_DDR4_LPDDR2_3_RON_38ohm (18) 141*4882a593Smuzhiyun #define PHY_DDR4_LPDDR2_3_RON_34ohm (19) 142*4882a593Smuzhiyun #define PHY_DDR4_LPDDR2_3_RON_31ohm (20) 143*4882a593Smuzhiyun #define PHY_DDR4_LPDDR2_3_RON_29ohm (21) 144*4882a593Smuzhiyun #define PHY_DDR4_LPDDR2_3_RON_27ohm (22) 145*4882a593Smuzhiyun #define PHY_DDR4_LPDDR2_3_RON_25ohm (23) 146*4882a593Smuzhiyun #define PHY_DDR4_LPDDR2_3_RON_23ohm (24) 147*4882a593Smuzhiyun #define PHY_DDR4_LPDDR2_3_RON_22ohm (25) 148*4882a593Smuzhiyun #define PHY_DDR4_LPDDR2_3_RON_21ohm (26) 149*4882a593Smuzhiyun #define PHY_DDR4_LPDDR2_3_RON_20ohm (27) 150*4882a593Smuzhiyun #define PHY_DDR4_LPDDR2_3_RON_19ohm (28) 151*4882a593Smuzhiyun #define PHY_DDR4_LPDDR2_3_RON_18ohm (29) 152*4882a593Smuzhiyun #define PHY_DDR4_LPDDR2_3_RON_17ohm (30) 153*4882a593Smuzhiyun #define PHY_DDR4_LPDDR2_3_RON_16ohm (31) 154*4882a593Smuzhiyun 155*4882a593Smuzhiyun #define PHY_DDR4_LPDDR2_3_RTT_DISABLE (0) 156*4882a593Smuzhiyun #define PHY_DDR4_LPDDR2_3_RTT_915ohm (1) 157*4882a593Smuzhiyun #define PHY_DDR4_LPDDR2_3_RTT_458ohm (2) 158*4882a593Smuzhiyun #define PHY_DDR4_LPDDR2_3_RTT_305ohm (3) 159*4882a593Smuzhiyun #define PHY_DDR4_LPDDR2_3_RTT_229ohm (4) 160*4882a593Smuzhiyun #define PHY_DDR4_LPDDR2_3_RTT_183ohm (5) 161*4882a593Smuzhiyun #define PHY_DDR4_LPDDR2_3_RTT_153ohm (6) 162*4882a593Smuzhiyun #define PHY_DDR4_LPDDR2_3_RTT_131ohm (7) 163*4882a593Smuzhiyun #define PHY_DDR4_LPDDR2_3_RTT_115ohm (16) 164*4882a593Smuzhiyun #define PHY_DDR4_LPDDR2_3_RTT_102ohm (17) 165*4882a593Smuzhiyun #define PHY_DDR4_LPDDR2_3_RTT_92ohm (18) 166*4882a593Smuzhiyun #define PHY_DDR4_LPDDR2_3_RTT_83ohm (19) 167*4882a593Smuzhiyun #define PHY_DDR4_LPDDR2_3_RTT_76ohm (20) 168*4882a593Smuzhiyun #define PHY_DDR4_LPDDR2_3_RTT_70ohm (21) 169*4882a593Smuzhiyun #define PHY_DDR4_LPDDR2_3_RTT_65ohm (22) 170*4882a593Smuzhiyun #define PHY_DDR4_LPDDR2_3_RTT_61ohm (23) 171*4882a593Smuzhiyun #define PHY_DDR4_LPDDR2_3_RTT_57ohm (24) 172*4882a593Smuzhiyun #define PHY_DDR4_LPDDR2_3_RTT_54ohm (25) 173*4882a593Smuzhiyun #define PHY_DDR4_LPDDR2_3_RTT_51ohm (26) 174*4882a593Smuzhiyun #define PHY_DDR4_LPDDR2_3_RTT_48ohm (27) 175*4882a593Smuzhiyun #define PHY_DDR4_LPDDR2_3_RTT_46ohm (28) 176*4882a593Smuzhiyun #define PHY_DDR4_LPDDR2_3_RTT_44ohm (29) 177*4882a593Smuzhiyun #define PHY_DDR4_LPDDR2_3_RTT_42ohm (30) 178*4882a593Smuzhiyun #define PHY_DDR4_LPDDR2_3_RTT_40ohm (31) 179*4882a593Smuzhiyun 180*4882a593Smuzhiyun #endif /*_DT_BINDINGS_DRAM_ROCKCHIP_RK1808_H*/ 181