1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (c) 2020 MediaTek Inc. 4*4882a593Smuzhiyun * Author: Yong Wu <yong.wu@mediatek.com> 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun #ifndef __DT_BINDINGS_MEMORY_MTK_MEMORY_PORT_H_ 7*4882a593Smuzhiyun #define __DT_BINDINGS_MEMORY_MTK_MEMORY_PORT_H_ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #define MTK_LARB_NR_MAX 32 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #define MTK_M4U_ID(larb, port) (((larb) << 5) | (port)) 12*4882a593Smuzhiyun #define MTK_M4U_TO_LARB(id) (((id) >> 5) & 0x1f) 13*4882a593Smuzhiyun #define MTK_M4U_TO_PORT(id) ((id) & 0x1f) 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun #endif 16