1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (c) 2018 MediaTek Inc. 4*4882a593Smuzhiyun * Author: Yong Wu <yong.wu@mediatek.com> 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun #ifndef _DT_BINDINGS_MEMORY_MT8183_LARB_PORT_H_ 7*4882a593Smuzhiyun #define _DT_BINDINGS_MEMORY_MT8183_LARB_PORT_H_ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #include <dt-bindings/memory/mtk-memory-port.h> 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #define M4U_LARB0_ID 0 12*4882a593Smuzhiyun #define M4U_LARB1_ID 1 13*4882a593Smuzhiyun #define M4U_LARB2_ID 2 14*4882a593Smuzhiyun #define M4U_LARB3_ID 3 15*4882a593Smuzhiyun #define M4U_LARB4_ID 4 16*4882a593Smuzhiyun #define M4U_LARB5_ID 5 17*4882a593Smuzhiyun #define M4U_LARB6_ID 6 18*4882a593Smuzhiyun #define M4U_LARB7_ID 7 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun /* larb0 */ 21*4882a593Smuzhiyun #define M4U_PORT_DISP_OVL0 MTK_M4U_ID(M4U_LARB0_ID, 0) 22*4882a593Smuzhiyun #define M4U_PORT_DISP_2L_OVL0_LARB0 MTK_M4U_ID(M4U_LARB0_ID, 1) 23*4882a593Smuzhiyun #define M4U_PORT_DISP_2L_OVL1_LARB0 MTK_M4U_ID(M4U_LARB0_ID, 2) 24*4882a593Smuzhiyun #define M4U_PORT_DISP_RDMA0 MTK_M4U_ID(M4U_LARB0_ID, 3) 25*4882a593Smuzhiyun #define M4U_PORT_DISP_RDMA1 MTK_M4U_ID(M4U_LARB0_ID, 4) 26*4882a593Smuzhiyun #define M4U_PORT_DISP_WDMA0 MTK_M4U_ID(M4U_LARB0_ID, 5) 27*4882a593Smuzhiyun #define M4U_PORT_MDP_RDMA0 MTK_M4U_ID(M4U_LARB0_ID, 6) 28*4882a593Smuzhiyun #define M4U_PORT_MDP_WROT0 MTK_M4U_ID(M4U_LARB0_ID, 7) 29*4882a593Smuzhiyun #define M4U_PORT_MDP_WDMA0 MTK_M4U_ID(M4U_LARB0_ID, 8) 30*4882a593Smuzhiyun #define M4U_PORT_DISP_FAKE0 MTK_M4U_ID(M4U_LARB0_ID, 9) 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun /* larb1 */ 33*4882a593Smuzhiyun #define M4U_PORT_HW_VDEC_MC_EXT MTK_M4U_ID(M4U_LARB1_ID, 0) 34*4882a593Smuzhiyun #define M4U_PORT_HW_VDEC_PP_EXT MTK_M4U_ID(M4U_LARB1_ID, 1) 35*4882a593Smuzhiyun #define M4U_PORT_HW_VDEC_VLD_EXT MTK_M4U_ID(M4U_LARB1_ID, 2) 36*4882a593Smuzhiyun #define M4U_PORT_HW_VDEC_AVC_MV_EXT MTK_M4U_ID(M4U_LARB1_ID, 3) 37*4882a593Smuzhiyun #define M4U_PORT_HW_VDEC_PRED_RD_EXT MTK_M4U_ID(M4U_LARB1_ID, 4) 38*4882a593Smuzhiyun #define M4U_PORT_HW_VDEC_PRED_WR_EXT MTK_M4U_ID(M4U_LARB1_ID, 5) 39*4882a593Smuzhiyun #define M4U_PORT_HW_VDEC_PPWRAP_EXT MTK_M4U_ID(M4U_LARB1_ID, 6) 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun /* larb2 VPU0 */ 42*4882a593Smuzhiyun #define M4U_PORT_IMG_IPUO MTK_M4U_ID(M4U_LARB2_ID, 0) 43*4882a593Smuzhiyun #define M4U_PORT_IMG_IPU3O MTK_M4U_ID(M4U_LARB2_ID, 1) 44*4882a593Smuzhiyun #define M4U_PORT_IMG_IPUI MTK_M4U_ID(M4U_LARB2_ID, 2) 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun /* larb3 VPU1 */ 47*4882a593Smuzhiyun #define M4U_PORT_CAM_IPUO MTK_M4U_ID(M4U_LARB3_ID, 0) 48*4882a593Smuzhiyun #define M4U_PORT_CAM_IPU2O MTK_M4U_ID(M4U_LARB3_ID, 1) 49*4882a593Smuzhiyun #define M4U_PORT_CAM_IPU3O MTK_M4U_ID(M4U_LARB3_ID, 2) 50*4882a593Smuzhiyun #define M4U_PORT_CAM_IPUI MTK_M4U_ID(M4U_LARB3_ID, 3) 51*4882a593Smuzhiyun #define M4U_PORT_CAM_IPU2I MTK_M4U_ID(M4U_LARB3_ID, 4) 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun /* larb4 */ 54*4882a593Smuzhiyun #define M4U_PORT_VENC_RCPU MTK_M4U_ID(M4U_LARB4_ID, 0) 55*4882a593Smuzhiyun #define M4U_PORT_VENC_REC MTK_M4U_ID(M4U_LARB4_ID, 1) 56*4882a593Smuzhiyun #define M4U_PORT_VENC_BSDMA MTK_M4U_ID(M4U_LARB4_ID, 2) 57*4882a593Smuzhiyun #define M4U_PORT_VENC_SV_COMV MTK_M4U_ID(M4U_LARB4_ID, 3) 58*4882a593Smuzhiyun #define M4U_PORT_VENC_RD_COMV MTK_M4U_ID(M4U_LARB4_ID, 4) 59*4882a593Smuzhiyun #define M4U_PORT_JPGENC_RDMA MTK_M4U_ID(M4U_LARB4_ID, 5) 60*4882a593Smuzhiyun #define M4U_PORT_JPGENC_BSDMA MTK_M4U_ID(M4U_LARB4_ID, 6) 61*4882a593Smuzhiyun #define M4U_PORT_VENC_CUR_LUMA MTK_M4U_ID(M4U_LARB4_ID, 7) 62*4882a593Smuzhiyun #define M4U_PORT_VENC_CUR_CHROMA MTK_M4U_ID(M4U_LARB4_ID, 8) 63*4882a593Smuzhiyun #define M4U_PORT_VENC_REF_LUMA MTK_M4U_ID(M4U_LARB4_ID, 9) 64*4882a593Smuzhiyun #define M4U_PORT_VENC_REF_CHROMA MTK_M4U_ID(M4U_LARB4_ID, 10) 65*4882a593Smuzhiyun 66*4882a593Smuzhiyun /* larb5 */ 67*4882a593Smuzhiyun #define M4U_PORT_CAM_IMGI MTK_M4U_ID(M4U_LARB5_ID, 0) 68*4882a593Smuzhiyun #define M4U_PORT_CAM_IMG2O MTK_M4U_ID(M4U_LARB5_ID, 1) 69*4882a593Smuzhiyun #define M4U_PORT_CAM_IMG3O MTK_M4U_ID(M4U_LARB5_ID, 2) 70*4882a593Smuzhiyun #define M4U_PORT_CAM_VIPI MTK_M4U_ID(M4U_LARB5_ID, 3) 71*4882a593Smuzhiyun #define M4U_PORT_CAM_LCEI MTK_M4U_ID(M4U_LARB5_ID, 4) 72*4882a593Smuzhiyun #define M4U_PORT_CAM_SMXI MTK_M4U_ID(M4U_LARB5_ID, 5) 73*4882a593Smuzhiyun #define M4U_PORT_CAM_SMXO MTK_M4U_ID(M4U_LARB5_ID, 6) 74*4882a593Smuzhiyun #define M4U_PORT_CAM_WPE0_RDMA1 MTK_M4U_ID(M4U_LARB5_ID, 7) 75*4882a593Smuzhiyun #define M4U_PORT_CAM_WPE0_RDMA0 MTK_M4U_ID(M4U_LARB5_ID, 8) 76*4882a593Smuzhiyun #define M4U_PORT_CAM_WPE0_WDMA MTK_M4U_ID(M4U_LARB5_ID, 9) 77*4882a593Smuzhiyun #define M4U_PORT_CAM_FDVT_RP MTK_M4U_ID(M4U_LARB5_ID, 10) 78*4882a593Smuzhiyun #define M4U_PORT_CAM_FDVT_WR MTK_M4U_ID(M4U_LARB5_ID, 11) 79*4882a593Smuzhiyun #define M4U_PORT_CAM_FDVT_RB MTK_M4U_ID(M4U_LARB5_ID, 12) 80*4882a593Smuzhiyun #define M4U_PORT_CAM_WPE1_RDMA0 MTK_M4U_ID(M4U_LARB5_ID, 13) 81*4882a593Smuzhiyun #define M4U_PORT_CAM_WPE1_RDMA1 MTK_M4U_ID(M4U_LARB5_ID, 14) 82*4882a593Smuzhiyun #define M4U_PORT_CAM_WPE1_WDMA MTK_M4U_ID(M4U_LARB5_ID, 15) 83*4882a593Smuzhiyun #define M4U_PORT_CAM_DPE_RDMA MTK_M4U_ID(M4U_LARB5_ID, 16) 84*4882a593Smuzhiyun #define M4U_PORT_CAM_DPE_WDMA MTK_M4U_ID(M4U_LARB5_ID, 17) 85*4882a593Smuzhiyun #define M4U_PORT_CAM_MFB_RDMA0 MTK_M4U_ID(M4U_LARB5_ID, 18) 86*4882a593Smuzhiyun #define M4U_PORT_CAM_MFB_RDMA1 MTK_M4U_ID(M4U_LARB5_ID, 19) 87*4882a593Smuzhiyun #define M4U_PORT_CAM_MFB_WDMA MTK_M4U_ID(M4U_LARB5_ID, 20) 88*4882a593Smuzhiyun #define M4U_PORT_CAM_RSC_RDMA0 MTK_M4U_ID(M4U_LARB5_ID, 21) 89*4882a593Smuzhiyun #define M4U_PORT_CAM_RSC_WDMA MTK_M4U_ID(M4U_LARB5_ID, 22) 90*4882a593Smuzhiyun #define M4U_PORT_CAM_OWE_RDMA MTK_M4U_ID(M4U_LARB5_ID, 23) 91*4882a593Smuzhiyun #define M4U_PORT_CAM_OWE_WDMA MTK_M4U_ID(M4U_LARB5_ID, 24) 92*4882a593Smuzhiyun 93*4882a593Smuzhiyun /* larb6 */ 94*4882a593Smuzhiyun #define M4U_PORT_CAM_IMGO MTK_M4U_ID(M4U_LARB6_ID, 0) 95*4882a593Smuzhiyun #define M4U_PORT_CAM_RRZO MTK_M4U_ID(M4U_LARB6_ID, 1) 96*4882a593Smuzhiyun #define M4U_PORT_CAM_AAO MTK_M4U_ID(M4U_LARB6_ID, 2) 97*4882a593Smuzhiyun #define M4U_PORT_CAM_AFO MTK_M4U_ID(M4U_LARB6_ID, 3) 98*4882a593Smuzhiyun #define M4U_PORT_CAM_LSCI0 MTK_M4U_ID(M4U_LARB6_ID, 4) 99*4882a593Smuzhiyun #define M4U_PORT_CAM_LSCI1 MTK_M4U_ID(M4U_LARB6_ID, 5) 100*4882a593Smuzhiyun #define M4U_PORT_CAM_PDO MTK_M4U_ID(M4U_LARB6_ID, 6) 101*4882a593Smuzhiyun #define M4U_PORT_CAM_BPCI MTK_M4U_ID(M4U_LARB6_ID, 7) 102*4882a593Smuzhiyun #define M4U_PORT_CAM_LCSO MTK_M4U_ID(M4U_LARB6_ID, 8) 103*4882a593Smuzhiyun #define M4U_PORT_CAM_CAM_RSSO_A MTK_M4U_ID(M4U_LARB6_ID, 9) 104*4882a593Smuzhiyun #define M4U_PORT_CAM_UFEO MTK_M4U_ID(M4U_LARB6_ID, 10) 105*4882a593Smuzhiyun #define M4U_PORT_CAM_SOCO MTK_M4U_ID(M4U_LARB6_ID, 11) 106*4882a593Smuzhiyun #define M4U_PORT_CAM_SOC1 MTK_M4U_ID(M4U_LARB6_ID, 12) 107*4882a593Smuzhiyun #define M4U_PORT_CAM_SOC2 MTK_M4U_ID(M4U_LARB6_ID, 13) 108*4882a593Smuzhiyun #define M4U_PORT_CAM_CCUI MTK_M4U_ID(M4U_LARB6_ID, 14) 109*4882a593Smuzhiyun #define M4U_PORT_CAM_CCUO MTK_M4U_ID(M4U_LARB6_ID, 15) 110*4882a593Smuzhiyun #define M4U_PORT_CAM_RAWI_A MTK_M4U_ID(M4U_LARB6_ID, 16) 111*4882a593Smuzhiyun #define M4U_PORT_CAM_CCUG MTK_M4U_ID(M4U_LARB6_ID, 17) 112*4882a593Smuzhiyun #define M4U_PORT_CAM_PSO MTK_M4U_ID(M4U_LARB6_ID, 18) 113*4882a593Smuzhiyun #define M4U_PORT_CAM_AFO_1 MTK_M4U_ID(M4U_LARB6_ID, 19) 114*4882a593Smuzhiyun #define M4U_PORT_CAM_LSCI_2 MTK_M4U_ID(M4U_LARB6_ID, 20) 115*4882a593Smuzhiyun #define M4U_PORT_CAM_PDI MTK_M4U_ID(M4U_LARB6_ID, 21) 116*4882a593Smuzhiyun #define M4U_PORT_CAM_FLKO MTK_M4U_ID(M4U_LARB6_ID, 22) 117*4882a593Smuzhiyun #define M4U_PORT_CAM_LMVO MTK_M4U_ID(M4U_LARB6_ID, 23) 118*4882a593Smuzhiyun #define M4U_PORT_CAM_UFGO MTK_M4U_ID(M4U_LARB6_ID, 24) 119*4882a593Smuzhiyun #define M4U_PORT_CAM_SPARE MTK_M4U_ID(M4U_LARB6_ID, 25) 120*4882a593Smuzhiyun #define M4U_PORT_CAM_SPARE_2 MTK_M4U_ID(M4U_LARB6_ID, 26) 121*4882a593Smuzhiyun #define M4U_PORT_CAM_SPARE_3 MTK_M4U_ID(M4U_LARB6_ID, 27) 122*4882a593Smuzhiyun #define M4U_PORT_CAM_SPARE_4 MTK_M4U_ID(M4U_LARB6_ID, 28) 123*4882a593Smuzhiyun #define M4U_PORT_CAM_SPARE_5 MTK_M4U_ID(M4U_LARB6_ID, 29) 124*4882a593Smuzhiyun #define M4U_PORT_CAM_SPARE_6 MTK_M4U_ID(M4U_LARB6_ID, 30) 125*4882a593Smuzhiyun 126*4882a593Smuzhiyun /* CCU */ 127*4882a593Smuzhiyun #define M4U_PORT_CCU0 MTK_M4U_ID(M4U_LARB7_ID, 0) 128*4882a593Smuzhiyun #define M4U_PORT_CCU1 MTK_M4U_ID(M4U_LARB7_ID, 1) 129*4882a593Smuzhiyun 130*4882a593Smuzhiyun #endif 131