1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (c) 2020 MediaTek Inc. 4*4882a593Smuzhiyun * Copyright (c) 2020 BayLibre, SAS 5*4882a593Smuzhiyun * Author: Honghui Zhang <honghui.zhang@mediatek.com> 6*4882a593Smuzhiyun * Author: Fabien Parent <fparent@baylibre.com> 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun #ifndef _DT_BINDINGS_MEMORY_MT8167_LARB_PORT_H_ 9*4882a593Smuzhiyun #define _DT_BINDINGS_MEMORY_MT8167_LARB_PORT_H_ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #include <dt-bindings/memory/mtk-memory-port.h> 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun #define M4U_LARB0_ID 0 14*4882a593Smuzhiyun #define M4U_LARB1_ID 1 15*4882a593Smuzhiyun #define M4U_LARB2_ID 2 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun /* larb0 */ 18*4882a593Smuzhiyun #define M4U_PORT_DISP_OVL0 MTK_M4U_ID(M4U_LARB0_ID, 0) 19*4882a593Smuzhiyun #define M4U_PORT_DISP_RDMA0 MTK_M4U_ID(M4U_LARB0_ID, 1) 20*4882a593Smuzhiyun #define M4U_PORT_DISP_WDMA0 MTK_M4U_ID(M4U_LARB0_ID, 2) 21*4882a593Smuzhiyun #define M4U_PORT_DISP_RDMA1 MTK_M4U_ID(M4U_LARB0_ID, 3) 22*4882a593Smuzhiyun #define M4U_PORT_MDP_RDMA MTK_M4U_ID(M4U_LARB0_ID, 4) 23*4882a593Smuzhiyun #define M4U_PORT_MDP_WDMA MTK_M4U_ID(M4U_LARB0_ID, 5) 24*4882a593Smuzhiyun #define M4U_PORT_MDP_WROT MTK_M4U_ID(M4U_LARB0_ID, 6) 25*4882a593Smuzhiyun #define M4U_PORT_DISP_FAKE MTK_M4U_ID(M4U_LARB0_ID, 7) 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun /* larb1*/ 28*4882a593Smuzhiyun #define M4U_PORT_CAM_IMGO MTK_M4U_ID(M4U_LARB1_ID, 0) 29*4882a593Smuzhiyun #define M4U_PORT_CAM_IMG2O MTK_M4U_ID(M4U_LARB1_ID, 1) 30*4882a593Smuzhiyun #define M4U_PORT_CAM_LSCI MTK_M4U_ID(M4U_LARB1_ID, 2) 31*4882a593Smuzhiyun #define M4U_PORT_CAM_ESFKO MTK_M4U_ID(M4U_LARB1_ID, 3) 32*4882a593Smuzhiyun #define M4U_PORT_CAM_AAO MTK_M4U_ID(M4U_LARB1_ID, 4) 33*4882a593Smuzhiyun #define M4U_PORT_VENC_REC MTK_M4U_ID(M4U_LARB1_ID, 5) 34*4882a593Smuzhiyun #define M4U_PORT_VENC_BSDMA MTK_M4U_ID(M4U_LARB1_ID, 6) 35*4882a593Smuzhiyun #define M4U_PORT_VENC_RD_COMV MTK_M4U_ID(M4U_LARB1_ID, 7) 36*4882a593Smuzhiyun #define M4U_PORT_CAM_IMGI MTK_M4U_ID(M4U_LARB1_ID, 8) 37*4882a593Smuzhiyun #define M4U_PORT_VENC_CUR_LUMA MTK_M4U_ID(M4U_LARB1_ID, 9) 38*4882a593Smuzhiyun #define M4U_PORT_VENC_CUR_CHROMA MTK_M4U_ID(M4U_LARB1_ID, 10) 39*4882a593Smuzhiyun #define M4U_PORT_VENC_REF_LUMA MTK_M4U_ID(M4U_LARB1_ID, 11) 40*4882a593Smuzhiyun #define M4U_PORT_VENC_REF_CHROMA MTK_M4U_ID(M4U_LARB1_ID, 12) 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun /* larb2*/ 43*4882a593Smuzhiyun #define M4U_PORT_HW_VDEC_MC_EXT MTK_M4U_ID(M4U_LARB2_ID, 0) 44*4882a593Smuzhiyun #define M4U_PORT_HW_VDEC_PP_EXT MTK_M4U_ID(M4U_LARB2_ID, 1) 45*4882a593Smuzhiyun #define M4U_PORT_HW_VDEC_VLD_EXT MTK_M4U_ID(M4U_LARB2_ID, 2) 46*4882a593Smuzhiyun #define M4U_PORT_HW_VDEC_AVC_MV_EXT MTK_M4U_ID(M4U_LARB2_ID, 3) 47*4882a593Smuzhiyun #define M4U_PORT_HW_VDEC_PRED_RD_EXT MTK_M4U_ID(M4U_LARB2_ID, 4) 48*4882a593Smuzhiyun #define M4U_PORT_HW_VDEC_PRED_WR_EXT MTK_M4U_ID(M4U_LARB2_ID, 5) 49*4882a593Smuzhiyun #define M4U_PORT_HW_VDEC_PPWRAP_EXT MTK_M4U_ID(M4U_LARB2_ID, 6) 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun #endif 52