1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (c) 2019 MediaTek Inc. 4*4882a593Smuzhiyun * Author: Chao Hao <chao.hao@mediatek.com> 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #ifndef _DT_BINDINGS_MEMORY_MT6779_LARB_PORT_H_ 8*4882a593Smuzhiyun #define _DT_BINDINGS_MEMORY_MT6779_LARB_PORT_H_ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #include <dt-bindings/memory/mtk-memory-port.h> 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #define M4U_LARB0_ID 0 13*4882a593Smuzhiyun #define M4U_LARB1_ID 1 14*4882a593Smuzhiyun #define M4U_LARB2_ID 2 15*4882a593Smuzhiyun #define M4U_LARB3_ID 3 16*4882a593Smuzhiyun #define M4U_LARB4_ID 4 17*4882a593Smuzhiyun #define M4U_LARB5_ID 5 18*4882a593Smuzhiyun #define M4U_LARB6_ID 6 19*4882a593Smuzhiyun #define M4U_LARB7_ID 7 20*4882a593Smuzhiyun #define M4U_LARB8_ID 8 21*4882a593Smuzhiyun #define M4U_LARB9_ID 9 22*4882a593Smuzhiyun #define M4U_LARB10_ID 10 23*4882a593Smuzhiyun #define M4U_LARB11_ID 11 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun /* larb0 */ 26*4882a593Smuzhiyun #define M4U_PORT_DISP_POSTMASK0 MTK_M4U_ID(M4U_LARB0_ID, 0) 27*4882a593Smuzhiyun #define M4U_PORT_DISP_OVL0_HDR MTK_M4U_ID(M4U_LARB0_ID, 1) 28*4882a593Smuzhiyun #define M4U_PORT_DISP_OVL1_HDR MTK_M4U_ID(M4U_LARB0_ID, 2) 29*4882a593Smuzhiyun #define M4U_PORT_DISP_OVL0 MTK_M4U_ID(M4U_LARB0_ID, 3) 30*4882a593Smuzhiyun #define M4U_PORT_DISP_OVL1 MTK_M4U_ID(M4U_LARB0_ID, 4) 31*4882a593Smuzhiyun #define M4U_PORT_DISP_PVRIC0 MTK_M4U_ID(M4U_LARB0_ID, 5) 32*4882a593Smuzhiyun #define M4U_PORT_DISP_RDMA0 MTK_M4U_ID(M4U_LARB0_ID, 6) 33*4882a593Smuzhiyun #define M4U_PORT_DISP_WDMA0 MTK_M4U_ID(M4U_LARB0_ID, 7) 34*4882a593Smuzhiyun #define M4U_PORT_DISP_FAKE0 MTK_M4U_ID(M4U_LARB0_ID, 8) 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun /* larb1 */ 37*4882a593Smuzhiyun #define M4U_PORT_DISP_OVL0_2L_HDR MTK_M4U_ID(M4U_LARB1_ID, 0) 38*4882a593Smuzhiyun #define M4U_PORT_DISP_OVL1_2L_HDR MTK_M4U_ID(M4U_LARB1_ID, 1) 39*4882a593Smuzhiyun #define M4U_PORT_DISP_OVL0_2L MTK_M4U_ID(M4U_LARB1_ID, 2) 40*4882a593Smuzhiyun #define M4U_PORT_DISP_OVL1_2L MTK_M4U_ID(M4U_LARB1_ID, 3) 41*4882a593Smuzhiyun #define M4U_PORT_DISP_RDMA1 MTK_M4U_ID(M4U_LARB1_ID, 4) 42*4882a593Smuzhiyun #define M4U_PORT_MDP_PVRIC0 MTK_M4U_ID(M4U_LARB1_ID, 5) 43*4882a593Smuzhiyun #define M4U_PORT_MDP_PVRIC1 MTK_M4U_ID(M4U_LARB1_ID, 6) 44*4882a593Smuzhiyun #define M4U_PORT_MDP_RDMA0 MTK_M4U_ID(M4U_LARB1_ID, 7) 45*4882a593Smuzhiyun #define M4U_PORT_MDP_RDMA1 MTK_M4U_ID(M4U_LARB1_ID, 8) 46*4882a593Smuzhiyun #define M4U_PORT_MDP_WROT0_R MTK_M4U_ID(M4U_LARB1_ID, 9) 47*4882a593Smuzhiyun #define M4U_PORT_MDP_WROT0_W MTK_M4U_ID(M4U_LARB1_ID, 10) 48*4882a593Smuzhiyun #define M4U_PORT_MDP_WROT1_R MTK_M4U_ID(M4U_LARB1_ID, 11) 49*4882a593Smuzhiyun #define M4U_PORT_MDP_WROT1_W MTK_M4U_ID(M4U_LARB1_ID, 12) 50*4882a593Smuzhiyun #define M4U_PORT_DISP_FAKE1 MTK_M4U_ID(M4U_LARB1_ID, 13) 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun /* larb2-VDEC */ 53*4882a593Smuzhiyun #define M4U_PORT_HW_VDEC_MC_EXT MTK_M4U_ID(M4U_LARB2_ID, 0) 54*4882a593Smuzhiyun #define M4U_PORT_HW_VDEC_UFO_EXT MTK_M4U_ID(M4U_LARB2_ID, 1) 55*4882a593Smuzhiyun #define M4U_PORT_HW_VDEC_PP_EXT MTK_M4U_ID(M4U_LARB2_ID, 2) 56*4882a593Smuzhiyun #define M4U_PORT_HW_VDEC_PRED_RD_EXT MTK_M4U_ID(M4U_LARB2_ID, 3) 57*4882a593Smuzhiyun #define M4U_PORT_HW_VDEC_PRED_WR_EXT MTK_M4U_ID(M4U_LARB2_ID, 4) 58*4882a593Smuzhiyun #define M4U_PORT_HW_VDEC_PPWRAP_EXT MTK_M4U_ID(M4U_LARB2_ID, 5) 59*4882a593Smuzhiyun #define M4U_PORT_HW_VDEC_TILE_EXT MTK_M4U_ID(M4U_LARB2_ID, 6) 60*4882a593Smuzhiyun #define M4U_PORT_HW_VDEC_VLD_EXT MTK_M4U_ID(M4U_LARB2_ID, 7) 61*4882a593Smuzhiyun #define M4U_PORT_HW_VDEC_VLD2_EXT MTK_M4U_ID(M4U_LARB2_ID, 8) 62*4882a593Smuzhiyun #define M4U_PORT_HW_VDEC_AVC_MV_EXT MTK_M4U_ID(M4U_LARB2_ID, 9) 63*4882a593Smuzhiyun #define M4U_PORT_HW_VDEC_UFO_ENC_EXT MTK_M4U_ID(M4U_LARB2_ID, 10) 64*4882a593Smuzhiyun #define M4U_PORT_HW_VDEC_RG_CTRL_DMA_EXT MTK_M4U_ID(M4U_LARB2_ID, 11) 65*4882a593Smuzhiyun 66*4882a593Smuzhiyun /* larb3-VENC */ 67*4882a593Smuzhiyun #define M4U_PORT_VENC_RCPU MTK_M4U_ID(M4U_LARB3_ID, 0) 68*4882a593Smuzhiyun #define M4U_PORT_VENC_REC MTK_M4U_ID(M4U_LARB3_ID, 1) 69*4882a593Smuzhiyun #define M4U_PORT_VENC_BSDMA MTK_M4U_ID(M4U_LARB3_ID, 2) 70*4882a593Smuzhiyun #define M4U_PORT_VENC_SV_COMV MTK_M4U_ID(M4U_LARB3_ID, 3) 71*4882a593Smuzhiyun #define M4U_PORT_VENC_RD_COMV MTK_M4U_ID(M4U_LARB3_ID, 4) 72*4882a593Smuzhiyun #define M4U_PORT_VENC_NBM_RDMA MTK_M4U_ID(M4U_LARB3_ID, 5) 73*4882a593Smuzhiyun #define M4U_PORT_VENC_NBM_RDMA_LITE MTK_M4U_ID(M4U_LARB3_ID, 6) 74*4882a593Smuzhiyun #define M4U_PORT_JPGENC_Y_RDMA MTK_M4U_ID(M4U_LARB3_ID, 7) 75*4882a593Smuzhiyun #define M4U_PORT_JPGENC_C_RDMA MTK_M4U_ID(M4U_LARB3_ID, 8) 76*4882a593Smuzhiyun #define M4U_PORT_JPGENC_Q_TABLE MTK_M4U_ID(M4U_LARB3_ID, 9) 77*4882a593Smuzhiyun #define M4U_PORT_JPGENC_BSDMA MTK_M4U_ID(M4U_LARB3_ID, 10) 78*4882a593Smuzhiyun #define M4U_PORT_JPGDEC_WDMA MTK_M4U_ID(M4U_LARB3_ID, 11) 79*4882a593Smuzhiyun #define M4U_PORT_JPGDEC_BSDMA MTK_M4U_ID(M4U_LARB3_ID, 12) 80*4882a593Smuzhiyun #define M4U_PORT_VENC_NBM_WDMA MTK_M4U_ID(M4U_LARB3_ID, 13) 81*4882a593Smuzhiyun #define M4U_PORT_VENC_NBM_WDMA_LITE MTK_M4U_ID(M4U_LARB3_ID, 14) 82*4882a593Smuzhiyun #define M4U_PORT_VENC_CUR_LUMA MTK_M4U_ID(M4U_LARB3_ID, 15) 83*4882a593Smuzhiyun #define M4U_PORT_VENC_CUR_CHROMA MTK_M4U_ID(M4U_LARB3_ID, 16) 84*4882a593Smuzhiyun #define M4U_PORT_VENC_REF_LUMA MTK_M4U_ID(M4U_LARB3_ID, 17) 85*4882a593Smuzhiyun #define M4U_PORT_VENC_REF_CHROMA MTK_M4U_ID(M4U_LARB3_ID, 18) 86*4882a593Smuzhiyun 87*4882a593Smuzhiyun /* larb4-dummy */ 88*4882a593Smuzhiyun 89*4882a593Smuzhiyun /* larb5-IMG */ 90*4882a593Smuzhiyun #define M4U_PORT_IMGI_D1 MTK_M4U_ID(M4U_LARB5_ID, 0) 91*4882a593Smuzhiyun #define M4U_PORT_IMGBI_D1 MTK_M4U_ID(M4U_LARB5_ID, 1) 92*4882a593Smuzhiyun #define M4U_PORT_DMGI_D1 MTK_M4U_ID(M4U_LARB5_ID, 2) 93*4882a593Smuzhiyun #define M4U_PORT_DEPI_D1 MTK_M4U_ID(M4U_LARB5_ID, 3) 94*4882a593Smuzhiyun #define M4U_PORT_LCEI_D1 MTK_M4U_ID(M4U_LARB5_ID, 4) 95*4882a593Smuzhiyun #define M4U_PORT_SMTI_D1 MTK_M4U_ID(M4U_LARB5_ID, 5) 96*4882a593Smuzhiyun #define M4U_PORT_SMTO_D2 MTK_M4U_ID(M4U_LARB5_ID, 6) 97*4882a593Smuzhiyun #define M4U_PORT_SMTO_D1 MTK_M4U_ID(M4U_LARB5_ID, 7) 98*4882a593Smuzhiyun #define M4U_PORT_CRZO_D1 MTK_M4U_ID(M4U_LARB5_ID, 8) 99*4882a593Smuzhiyun #define M4U_PORT_IMG3O_D1 MTK_M4U_ID(M4U_LARB5_ID, 9) 100*4882a593Smuzhiyun #define M4U_PORT_VIPI_D1 MTK_M4U_ID(M4U_LARB5_ID, 10) 101*4882a593Smuzhiyun #define M4U_PORT_WPE_RDMA1 MTK_M4U_ID(M4U_LARB5_ID, 11) 102*4882a593Smuzhiyun #define M4U_PORT_WPE_RDMA0 MTK_M4U_ID(M4U_LARB5_ID, 12) 103*4882a593Smuzhiyun #define M4U_PORT_WPE_WDMA MTK_M4U_ID(M4U_LARB5_ID, 13) 104*4882a593Smuzhiyun #define M4U_PORT_TIMGO_D1 MTK_M4U_ID(M4U_LARB5_ID, 14) 105*4882a593Smuzhiyun #define M4U_PORT_MFB_RDMA0 MTK_M4U_ID(M4U_LARB5_ID, 15) 106*4882a593Smuzhiyun #define M4U_PORT_MFB_RDMA1 MTK_M4U_ID(M4U_LARB5_ID, 16) 107*4882a593Smuzhiyun #define M4U_PORT_MFB_RDMA2 MTK_M4U_ID(M4U_LARB5_ID, 17) 108*4882a593Smuzhiyun #define M4U_PORT_MFB_RDMA3 MTK_M4U_ID(M4U_LARB5_ID, 18) 109*4882a593Smuzhiyun #define M4U_PORT_MFB_WDMA MTK_M4U_ID(M4U_LARB5_ID, 19) 110*4882a593Smuzhiyun #define M4U_PORT_RESERVE1 MTK_M4U_ID(M4U_LARB5_ID, 20) 111*4882a593Smuzhiyun #define M4U_PORT_RESERVE2 MTK_M4U_ID(M4U_LARB5_ID, 21) 112*4882a593Smuzhiyun #define M4U_PORT_RESERVE3 MTK_M4U_ID(M4U_LARB5_ID, 22) 113*4882a593Smuzhiyun #define M4U_PORT_RESERVE4 MTK_M4U_ID(M4U_LARB5_ID, 23) 114*4882a593Smuzhiyun #define M4U_PORT_RESERVE5 MTK_M4U_ID(M4U_LARB5_ID, 24) 115*4882a593Smuzhiyun #define M4U_PORT_RESERVE6 MTK_M4U_ID(M4U_LARB5_ID, 25) 116*4882a593Smuzhiyun 117*4882a593Smuzhiyun /* larb6-IMG-VPU */ 118*4882a593Smuzhiyun #define M4U_PORT_IMG_IPUO MTK_M4U_ID(M4U_LARB6_ID, 0) 119*4882a593Smuzhiyun #define M4U_PORT_IMG_IPU3O MTK_M4U_ID(M4U_LARB6_ID, 1) 120*4882a593Smuzhiyun #define M4U_PORT_IMG_IPUI MTK_M4U_ID(M4U_LARB6_ID, 2) 121*4882a593Smuzhiyun 122*4882a593Smuzhiyun /* larb7-DVS */ 123*4882a593Smuzhiyun #define M4U_PORT_DVS_RDMA MTK_M4U_ID(M4U_LARB7_ID, 0) 124*4882a593Smuzhiyun #define M4U_PORT_DVS_WDMA MTK_M4U_ID(M4U_LARB7_ID, 1) 125*4882a593Smuzhiyun #define M4U_PORT_DVP_RDMA MTK_M4U_ID(M4U_LARB7_ID, 2) 126*4882a593Smuzhiyun #define M4U_PORT_DVP_WDMA MTK_M4U_ID(M4U_LARB7_ID, 3) 127*4882a593Smuzhiyun 128*4882a593Smuzhiyun /* larb8-IPESYS */ 129*4882a593Smuzhiyun #define M4U_PORT_FDVT_RDA MTK_M4U_ID(M4U_LARB8_ID, 0) 130*4882a593Smuzhiyun #define M4U_PORT_FDVT_RDB MTK_M4U_ID(M4U_LARB8_ID, 1) 131*4882a593Smuzhiyun #define M4U_PORT_FDVT_WRA MTK_M4U_ID(M4U_LARB8_ID, 2) 132*4882a593Smuzhiyun #define M4U_PORT_FDVT_WRB MTK_M4U_ID(M4U_LARB8_ID, 3) 133*4882a593Smuzhiyun #define M4U_PORT_FE_RD0 MTK_M4U_ID(M4U_LARB8_ID, 4) 134*4882a593Smuzhiyun #define M4U_PORT_FE_RD1 MTK_M4U_ID(M4U_LARB8_ID, 5) 135*4882a593Smuzhiyun #define M4U_PORT_FE_WR0 MTK_M4U_ID(M4U_LARB8_ID, 6) 136*4882a593Smuzhiyun #define M4U_PORT_FE_WR1 MTK_M4U_ID(M4U_LARB8_ID, 7) 137*4882a593Smuzhiyun #define M4U_PORT_RSC_RDMA0 MTK_M4U_ID(M4U_LARB8_ID, 8) 138*4882a593Smuzhiyun #define M4U_PORT_RSC_WDMA MTK_M4U_ID(M4U_LARB8_ID, 9) 139*4882a593Smuzhiyun 140*4882a593Smuzhiyun /* larb9-CAM */ 141*4882a593Smuzhiyun #define M4U_PORT_CAM_IMGO_R1_C MTK_M4U_ID(M4U_LARB9_ID, 0) 142*4882a593Smuzhiyun #define M4U_PORT_CAM_RRZO_R1_C MTK_M4U_ID(M4U_LARB9_ID, 1) 143*4882a593Smuzhiyun #define M4U_PORT_CAM_LSCI_R1_C MTK_M4U_ID(M4U_LARB9_ID, 2) 144*4882a593Smuzhiyun #define M4U_PORT_CAM_BPCI_R1_C MTK_M4U_ID(M4U_LARB9_ID, 3) 145*4882a593Smuzhiyun #define M4U_PORT_CAM_YUVO_R1_C MTK_M4U_ID(M4U_LARB9_ID, 4) 146*4882a593Smuzhiyun #define M4U_PORT_CAM_UFDI_R2_C MTK_M4U_ID(M4U_LARB9_ID, 5) 147*4882a593Smuzhiyun #define M4U_PORT_CAM_RAWI_R2_C MTK_M4U_ID(M4U_LARB9_ID, 6) 148*4882a593Smuzhiyun #define M4U_PORT_CAM_RAWI_R5_C MTK_M4U_ID(M4U_LARB9_ID, 7) 149*4882a593Smuzhiyun #define M4U_PORT_CAM_CAMSV_1 MTK_M4U_ID(M4U_LARB9_ID, 8) 150*4882a593Smuzhiyun #define M4U_PORT_CAM_CAMSV_2 MTK_M4U_ID(M4U_LARB9_ID, 9) 151*4882a593Smuzhiyun #define M4U_PORT_CAM_CAMSV_3 MTK_M4U_ID(M4U_LARB9_ID, 10) 152*4882a593Smuzhiyun #define M4U_PORT_CAM_CAMSV_4 MTK_M4U_ID(M4U_LARB9_ID, 11) 153*4882a593Smuzhiyun #define M4U_PORT_CAM_CAMSV_5 MTK_M4U_ID(M4U_LARB9_ID, 12) 154*4882a593Smuzhiyun #define M4U_PORT_CAM_CAMSV_6 MTK_M4U_ID(M4U_LARB9_ID, 13) 155*4882a593Smuzhiyun #define M4U_PORT_CAM_AAO_R1_C MTK_M4U_ID(M4U_LARB9_ID, 14) 156*4882a593Smuzhiyun #define M4U_PORT_CAM_AFO_R1_C MTK_M4U_ID(M4U_LARB9_ID, 15) 157*4882a593Smuzhiyun #define M4U_PORT_CAM_FLKO_R1_C MTK_M4U_ID(M4U_LARB9_ID, 16) 158*4882a593Smuzhiyun #define M4U_PORT_CAM_LCESO_R1_C MTK_M4U_ID(M4U_LARB9_ID, 17) 159*4882a593Smuzhiyun #define M4U_PORT_CAM_CRZO_R1_C MTK_M4U_ID(M4U_LARB9_ID, 18) 160*4882a593Smuzhiyun #define M4U_PORT_CAM_LTMSO_R1_C MTK_M4U_ID(M4U_LARB9_ID, 19) 161*4882a593Smuzhiyun #define M4U_PORT_CAM_RSSO_R1_C MTK_M4U_ID(M4U_LARB9_ID, 20) 162*4882a593Smuzhiyun #define M4U_PORT_CAM_CCUI MTK_M4U_ID(M4U_LARB9_ID, 21) 163*4882a593Smuzhiyun #define M4U_PORT_CAM_CCUO MTK_M4U_ID(M4U_LARB9_ID, 22) 164*4882a593Smuzhiyun #define M4U_PORT_CAM_FAKE MTK_M4U_ID(M4U_LARB9_ID, 23) 165*4882a593Smuzhiyun 166*4882a593Smuzhiyun /* larb10-CAM_A */ 167*4882a593Smuzhiyun #define M4U_PORT_CAM_IMGO_R1_A MTK_M4U_ID(M4U_LARB10_ID, 0) 168*4882a593Smuzhiyun #define M4U_PORT_CAM_RRZO_R1_A MTK_M4U_ID(M4U_LARB10_ID, 1) 169*4882a593Smuzhiyun #define M4U_PORT_CAM_LSCI_R1_A MTK_M4U_ID(M4U_LARB10_ID, 2) 170*4882a593Smuzhiyun #define M4U_PORT_CAM_BPCI_R1_A MTK_M4U_ID(M4U_LARB10_ID, 3) 171*4882a593Smuzhiyun #define M4U_PORT_CAM_YUVO_R1_A MTK_M4U_ID(M4U_LARB10_ID, 4) 172*4882a593Smuzhiyun #define M4U_PORT_CAM_UFDI_R2_A MTK_M4U_ID(M4U_LARB10_ID, 5) 173*4882a593Smuzhiyun #define M4U_PORT_CAM_RAWI_R2_A MTK_M4U_ID(M4U_LARB10_ID, 6) 174*4882a593Smuzhiyun #define M4U_PORT_CAM_RAWI_R5_A MTK_M4U_ID(M4U_LARB10_ID, 7) 175*4882a593Smuzhiyun #define M4U_PORT_CAM_IMGO_R1_B MTK_M4U_ID(M4U_LARB10_ID, 8) 176*4882a593Smuzhiyun #define M4U_PORT_CAM_RRZO_R1_B MTK_M4U_ID(M4U_LARB10_ID, 9) 177*4882a593Smuzhiyun #define M4U_PORT_CAM_LSCI_R1_B MTK_M4U_ID(M4U_LARB10_ID, 10) 178*4882a593Smuzhiyun #define M4U_PORT_CAM_BPCI_R1_B MTK_M4U_ID(M4U_LARB10_ID, 11) 179*4882a593Smuzhiyun #define M4U_PORT_CAM_YUVO_R1_B MTK_M4U_ID(M4U_LARB10_ID, 12) 180*4882a593Smuzhiyun #define M4U_PORT_CAM_UFDI_R2_B MTK_M4U_ID(M4U_LARB10_ID, 13) 181*4882a593Smuzhiyun #define M4U_PORT_CAM_RAWI_R2_B MTK_M4U_ID(M4U_LARB10_ID, 14) 182*4882a593Smuzhiyun #define M4U_PORT_CAM_RAWI_R5_B MTK_M4U_ID(M4U_LARB10_ID, 15) 183*4882a593Smuzhiyun #define M4U_PORT_CAM_CAMSV_0 MTK_M4U_ID(M4U_LARB10_ID, 16) 184*4882a593Smuzhiyun #define M4U_PORT_CAM_AAO_R1_A MTK_M4U_ID(M4U_LARB10_ID, 17) 185*4882a593Smuzhiyun #define M4U_PORT_CAM_AFO_R1_A MTK_M4U_ID(M4U_LARB10_ID, 18) 186*4882a593Smuzhiyun #define M4U_PORT_CAM_FLKO_R1_A MTK_M4U_ID(M4U_LARB10_ID, 19) 187*4882a593Smuzhiyun #define M4U_PORT_CAM_LCESO_R1_A MTK_M4U_ID(M4U_LARB10_ID, 20) 188*4882a593Smuzhiyun #define M4U_PORT_CAM_CRZO_R1_A MTK_M4U_ID(M4U_LARB10_ID, 21) 189*4882a593Smuzhiyun #define M4U_PORT_CAM_AAO_R1_B MTK_M4U_ID(M4U_LARB10_ID, 22) 190*4882a593Smuzhiyun #define M4U_PORT_CAM_AFO_R1_B MTK_M4U_ID(M4U_LARB10_ID, 23) 191*4882a593Smuzhiyun #define M4U_PORT_CAM_FLKO_R1_B MTK_M4U_ID(M4U_LARB10_ID, 24) 192*4882a593Smuzhiyun #define M4U_PORT_CAM_LCESO_R1_B MTK_M4U_ID(M4U_LARB10_ID, 25) 193*4882a593Smuzhiyun #define M4U_PORT_CAM_CRZO_R1_B MTK_M4U_ID(M4U_LARB10_ID, 26) 194*4882a593Smuzhiyun #define M4U_PORT_CAM_LTMSO_R1_A MTK_M4U_ID(M4U_LARB10_ID, 27) 195*4882a593Smuzhiyun #define M4U_PORT_CAM_RSSO_R1_A MTK_M4U_ID(M4U_LARB10_ID, 28) 196*4882a593Smuzhiyun #define M4U_PORT_CAM_LTMSO_R1_B MTK_M4U_ID(M4U_LARB10_ID, 29) 197*4882a593Smuzhiyun #define M4U_PORT_CAM_RSSO_R1_B MTK_M4U_ID(M4U_LARB10_ID, 30) 198*4882a593Smuzhiyun 199*4882a593Smuzhiyun /* larb11-CAM-VPU */ 200*4882a593Smuzhiyun #define M4U_PORT_CAM_IPUO MTK_M4U_ID(M4U_LARB11_ID, 0) 201*4882a593Smuzhiyun #define M4U_PORT_CAM_IPU2O MTK_M4U_ID(M4U_LARB11_ID, 1) 202*4882a593Smuzhiyun #define M4U_PORT_CAM_IPU3O MTK_M4U_ID(M4U_LARB11_ID, 2) 203*4882a593Smuzhiyun #define M4U_PORT_CAM_IPUI MTK_M4U_ID(M4U_LARB11_ID, 3) 204*4882a593Smuzhiyun #define M4U_PORT_CAM_IPU2I MTK_M4U_ID(M4U_LARB11_ID, 4) 205*4882a593Smuzhiyun 206*4882a593Smuzhiyun #endif 207