1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (c) 2017 MediaTek Inc. 4*4882a593Smuzhiyun * Author: Yong Wu <yong.wu@mediatek.com> 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun #ifndef _DT_BINDINGS_MEMORY_MT2712_LARB_PORT_H_ 7*4882a593Smuzhiyun #define _DT_BINDINGS_MEMORY_MT2712_LARB_PORT_H_ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #include <dt-bindings/memory/mtk-memory-port.h> 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #define M4U_LARB0_ID 0 12*4882a593Smuzhiyun #define M4U_LARB1_ID 1 13*4882a593Smuzhiyun #define M4U_LARB2_ID 2 14*4882a593Smuzhiyun #define M4U_LARB3_ID 3 15*4882a593Smuzhiyun #define M4U_LARB4_ID 4 16*4882a593Smuzhiyun #define M4U_LARB5_ID 5 17*4882a593Smuzhiyun #define M4U_LARB6_ID 6 18*4882a593Smuzhiyun #define M4U_LARB7_ID 7 19*4882a593Smuzhiyun #define M4U_LARB8_ID 8 20*4882a593Smuzhiyun #define M4U_LARB9_ID 9 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun /* larb0 */ 23*4882a593Smuzhiyun #define M4U_PORT_DISP_OVL0 MTK_M4U_ID(M4U_LARB0_ID, 0) 24*4882a593Smuzhiyun #define M4U_PORT_DISP_RDMA0 MTK_M4U_ID(M4U_LARB0_ID, 1) 25*4882a593Smuzhiyun #define M4U_PORT_DISP_WDMA0 MTK_M4U_ID(M4U_LARB0_ID, 2) 26*4882a593Smuzhiyun #define M4U_PORT_DISP_OD_R MTK_M4U_ID(M4U_LARB0_ID, 3) 27*4882a593Smuzhiyun #define M4U_PORT_DISP_OD_W MTK_M4U_ID(M4U_LARB0_ID, 4) 28*4882a593Smuzhiyun #define M4U_PORT_MDP_RDMA0 MTK_M4U_ID(M4U_LARB0_ID, 5) 29*4882a593Smuzhiyun #define M4U_PORT_MDP_WDMA MTK_M4U_ID(M4U_LARB0_ID, 6) 30*4882a593Smuzhiyun #define M4U_PORT_DISP_RDMA2 MTK_M4U_ID(M4U_LARB0_ID, 7) 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun /* larb1 */ 33*4882a593Smuzhiyun #define M4U_PORT_HW_VDEC_MC_EXT MTK_M4U_ID(M4U_LARB1_ID, 0) 34*4882a593Smuzhiyun #define M4U_PORT_HW_VDEC_PP_EXT MTK_M4U_ID(M4U_LARB1_ID, 1) 35*4882a593Smuzhiyun #define M4U_PORT_HW_VDEC_UFO_EXT MTK_M4U_ID(M4U_LARB1_ID, 2) 36*4882a593Smuzhiyun #define M4U_PORT_HW_VDEC_VLD_EXT MTK_M4U_ID(M4U_LARB1_ID, 3) 37*4882a593Smuzhiyun #define M4U_PORT_HW_VDEC_VLD2_EXT MTK_M4U_ID(M4U_LARB1_ID, 4) 38*4882a593Smuzhiyun #define M4U_PORT_HW_VDEC_AVC_MV_EXT MTK_M4U_ID(M4U_LARB1_ID, 5) 39*4882a593Smuzhiyun #define M4U_PORT_HW_VDEC_PRED_RD_EXT MTK_M4U_ID(M4U_LARB1_ID, 6) 40*4882a593Smuzhiyun #define M4U_PORT_HW_VDEC_PRED_WR_EXT MTK_M4U_ID(M4U_LARB1_ID, 7) 41*4882a593Smuzhiyun #define M4U_PORT_HW_VDEC_PPWRAP_EXT MTK_M4U_ID(M4U_LARB1_ID, 8) 42*4882a593Smuzhiyun #define M4U_PORT_HW_VDEC_TILE MTK_M4U_ID(M4U_LARB1_ID, 9) 43*4882a593Smuzhiyun #define M4U_PORT_HW_IMG_RESZ_EXT MTK_M4U_ID(M4U_LARB1_ID, 10) 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun /* larb2 */ 46*4882a593Smuzhiyun #define M4U_PORT_CAM_DMA0 MTK_M4U_ID(M4U_LARB2_ID, 0) 47*4882a593Smuzhiyun #define M4U_PORT_CAM_DMA1 MTK_M4U_ID(M4U_LARB2_ID, 1) 48*4882a593Smuzhiyun #define M4U_PORT_CAM_DMA2 MTK_M4U_ID(M4U_LARB2_ID, 2) 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun /* larb3 */ 51*4882a593Smuzhiyun #define M4U_PORT_VENC_RCPU MTK_M4U_ID(M4U_LARB3_ID, 0) 52*4882a593Smuzhiyun #define M4U_PORT_VENC_REC MTK_M4U_ID(M4U_LARB3_ID, 1) 53*4882a593Smuzhiyun #define M4U_PORT_VENC_BSDMA MTK_M4U_ID(M4U_LARB3_ID, 2) 54*4882a593Smuzhiyun #define M4U_PORT_VENC_SV_COMV MTK_M4U_ID(M4U_LARB3_ID, 3) 55*4882a593Smuzhiyun #define M4U_PORT_VENC_RD_COMV MTK_M4U_ID(M4U_LARB3_ID, 4) 56*4882a593Smuzhiyun #define M4U_PORT_VENC_CUR_CHROMA MTK_M4U_ID(M4U_LARB3_ID, 5) 57*4882a593Smuzhiyun #define M4U_PORT_VENC_REF_CHROMA MTK_M4U_ID(M4U_LARB3_ID, 6) 58*4882a593Smuzhiyun #define M4U_PORT_VENC_CUR_LUMA MTK_M4U_ID(M4U_LARB3_ID, 7) 59*4882a593Smuzhiyun #define M4U_PORT_VENC_REF_LUMA MTK_M4U_ID(M4U_LARB3_ID, 8) 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun /* larb4 */ 62*4882a593Smuzhiyun #define M4U_PORT_DISP_OVL1 MTK_M4U_ID(M4U_LARB4_ID, 0) 63*4882a593Smuzhiyun #define M4U_PORT_DISP_RDMA1 MTK_M4U_ID(M4U_LARB4_ID, 1) 64*4882a593Smuzhiyun #define M4U_PORT_DISP_WDMA1 MTK_M4U_ID(M4U_LARB4_ID, 2) 65*4882a593Smuzhiyun #define M4U_PORT_DISP_OD1_R MTK_M4U_ID(M4U_LARB4_ID, 3) 66*4882a593Smuzhiyun #define M4U_PORT_DISP_OD1_W MTK_M4U_ID(M4U_LARB4_ID, 4) 67*4882a593Smuzhiyun #define M4U_PORT_MDP_RDMA1 MTK_M4U_ID(M4U_LARB4_ID, 5) 68*4882a593Smuzhiyun #define M4U_PORT_MDP_WROT1 MTK_M4U_ID(M4U_LARB4_ID, 6) 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun /* larb5 */ 71*4882a593Smuzhiyun #define M4U_PORT_DISP_OVL2 MTK_M4U_ID(M4U_LARB5_ID, 0) 72*4882a593Smuzhiyun #define M4U_PORT_DISP_WDMA2 MTK_M4U_ID(M4U_LARB5_ID, 1) 73*4882a593Smuzhiyun #define M4U_PORT_MDP_RDMA2 MTK_M4U_ID(M4U_LARB5_ID, 2) 74*4882a593Smuzhiyun #define M4U_PORT_MDP_WROT0 MTK_M4U_ID(M4U_LARB5_ID, 3) 75*4882a593Smuzhiyun 76*4882a593Smuzhiyun /* larb6 */ 77*4882a593Smuzhiyun #define M4U_PORT_JPGDEC_WDMA_0 MTK_M4U_ID(M4U_LARB6_ID, 0) 78*4882a593Smuzhiyun #define M4U_PORT_JPGDEC_WDMA_1 MTK_M4U_ID(M4U_LARB6_ID, 1) 79*4882a593Smuzhiyun #define M4U_PORT_JPGDEC_BSDMA_0 MTK_M4U_ID(M4U_LARB6_ID, 2) 80*4882a593Smuzhiyun #define M4U_PORT_JPGDEC_BSDMA_1 MTK_M4U_ID(M4U_LARB6_ID, 3) 81*4882a593Smuzhiyun 82*4882a593Smuzhiyun /* larb7 */ 83*4882a593Smuzhiyun #define M4U_PORT_MDP_RDMA3 MTK_M4U_ID(M4U_LARB7_ID, 0) 84*4882a593Smuzhiyun #define M4U_PORT_MDP_WROT2 MTK_M4U_ID(M4U_LARB7_ID, 1) 85*4882a593Smuzhiyun 86*4882a593Smuzhiyun /* larb8 */ 87*4882a593Smuzhiyun #define M4U_PORT_VDO MTK_M4U_ID(M4U_LARB8_ID, 0) 88*4882a593Smuzhiyun #define M4U_PORT_NR MTK_M4U_ID(M4U_LARB8_ID, 1) 89*4882a593Smuzhiyun #define M4U_PORT_WR_CHANNEL0 MTK_M4U_ID(M4U_LARB8_ID, 2) 90*4882a593Smuzhiyun 91*4882a593Smuzhiyun /* larb9 */ 92*4882a593Smuzhiyun #define M4U_PORT_TVD MTK_M4U_ID(M4U_LARB9_ID, 0) 93*4882a593Smuzhiyun #define M4U_PORT_WR_CHANNEL1 MTK_M4U_ID(M4U_LARB9_ID, 1) 94*4882a593Smuzhiyun 95*4882a593Smuzhiyun #endif 96