1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Xilinx Video IP Core 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 2013-2015 Ideas on Board 6*4882a593Smuzhiyun * Copyright (C) 2013-2015 Xilinx, Inc. 7*4882a593Smuzhiyun * 8*4882a593Smuzhiyun * Contacts: Hyun Kwon <hyun.kwon@xilinx.com> 9*4882a593Smuzhiyun * Laurent Pinchart <laurent.pinchart@ideasonboard.com> 10*4882a593Smuzhiyun */ 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #ifndef __DT_BINDINGS_MEDIA_XILINX_VIP_H__ 13*4882a593Smuzhiyun #define __DT_BINDINGS_MEDIA_XILINX_VIP_H__ 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun /* 16*4882a593Smuzhiyun * Video format codes as defined in "AXI4-Stream Video IP and System Design 17*4882a593Smuzhiyun * Guide". 18*4882a593Smuzhiyun */ 19*4882a593Smuzhiyun #define XVIP_VF_YUV_422 0 20*4882a593Smuzhiyun #define XVIP_VF_YUV_444 1 21*4882a593Smuzhiyun #define XVIP_VF_RBG 2 22*4882a593Smuzhiyun #define XVIP_VF_YUV_420 3 23*4882a593Smuzhiyun #define XVIP_VF_YUVA_422 4 24*4882a593Smuzhiyun #define XVIP_VF_YUVA_444 5 25*4882a593Smuzhiyun #define XVIP_VF_RGBA 6 26*4882a593Smuzhiyun #define XVIP_VF_YUVA_420 7 27*4882a593Smuzhiyun #define XVIP_VF_YUVD_422 8 28*4882a593Smuzhiyun #define XVIP_VF_YUVD_444 9 29*4882a593Smuzhiyun #define XVIP_VF_RGBD 10 30*4882a593Smuzhiyun #define XVIP_VF_YUVD_420 11 31*4882a593Smuzhiyun #define XVIP_VF_MONO_SENSOR 12 32*4882a593Smuzhiyun #define XVIP_VF_CUSTOM2 13 33*4882a593Smuzhiyun #define XVIP_VF_CUSTOM3 14 34*4882a593Smuzhiyun #define XVIP_VF_CUSTOM4 15 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun #endif /* __DT_BINDINGS_MEDIA_XILINX_VIP_H__ */ 37