1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * This header provides constants for binding nvidia,tegra186-hsp. 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun #ifndef _DT_BINDINGS_MAILBOX_TEGRA186_HSP_H 7*4882a593Smuzhiyun #define _DT_BINDINGS_MAILBOX_TEGRA186_HSP_H 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun /* 10*4882a593Smuzhiyun * These define the type of mailbox that is to be used (doorbell, shared 11*4882a593Smuzhiyun * mailbox, shared semaphore or arbitrated semaphore). 12*4882a593Smuzhiyun */ 13*4882a593Smuzhiyun #define TEGRA_HSP_MBOX_TYPE_DB 0x0 14*4882a593Smuzhiyun #define TEGRA_HSP_MBOX_TYPE_SM 0x1 15*4882a593Smuzhiyun #define TEGRA_HSP_MBOX_TYPE_SS 0x2 16*4882a593Smuzhiyun #define TEGRA_HSP_MBOX_TYPE_AS 0x3 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun /* 19*4882a593Smuzhiyun * These defines represent the bit associated with the given master ID in the 20*4882a593Smuzhiyun * doorbell registers. 21*4882a593Smuzhiyun */ 22*4882a593Smuzhiyun #define TEGRA_HSP_DB_MASTER_CCPLEX 17 23*4882a593Smuzhiyun #define TEGRA_HSP_DB_MASTER_BPMP 19 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun /* 26*4882a593Smuzhiyun * Shared mailboxes are unidirectional, so the direction needs to be specified 27*4882a593Smuzhiyun * in the device tree. 28*4882a593Smuzhiyun */ 29*4882a593Smuzhiyun #define TEGRA_HSP_SM_MASK 0x00ffffff 30*4882a593Smuzhiyun #define TEGRA_HSP_SM_FLAG_RX (0 << 31) 31*4882a593Smuzhiyun #define TEGRA_HSP_SM_FLAG_TX (1 << 31) 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun #define TEGRA_HSP_SM_RX(x) (TEGRA_HSP_SM_FLAG_RX | ((x) & TEGRA_HSP_SM_MASK)) 34*4882a593Smuzhiyun #define TEGRA_HSP_SM_TX(x) (TEGRA_HSP_SM_FLAG_TX | ((x) & TEGRA_HSP_SM_MASK)) 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun #endif 37