1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Qualcomm SC7180 interconnect IDs 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (c) 2020, The Linux Foundation. All rights reserved. 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #ifndef __DT_BINDINGS_INTERCONNECT_QCOM_SC7180_H 9*4882a593Smuzhiyun #define __DT_BINDINGS_INTERCONNECT_QCOM_SC7180_H 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #define MASTER_A1NOC_CFG 0 12*4882a593Smuzhiyun #define MASTER_QSPI 1 13*4882a593Smuzhiyun #define MASTER_QUP_0 2 14*4882a593Smuzhiyun #define MASTER_SDCC_2 3 15*4882a593Smuzhiyun #define MASTER_EMMC 4 16*4882a593Smuzhiyun #define MASTER_UFS_MEM 5 17*4882a593Smuzhiyun #define SLAVE_A1NOC_SNOC 6 18*4882a593Smuzhiyun #define SLAVE_SERVICE_A1NOC 7 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun #define MASTER_A2NOC_CFG 0 21*4882a593Smuzhiyun #define MASTER_QDSS_BAM 1 22*4882a593Smuzhiyun #define MASTER_QUP_1 2 23*4882a593Smuzhiyun #define MASTER_USB3 3 24*4882a593Smuzhiyun #define MASTER_CRYPTO 4 25*4882a593Smuzhiyun #define MASTER_IPA 5 26*4882a593Smuzhiyun #define MASTER_QDSS_ETR 6 27*4882a593Smuzhiyun #define SLAVE_A2NOC_SNOC 7 28*4882a593Smuzhiyun #define SLAVE_SERVICE_A2NOC 8 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun #define MASTER_CAMNOC_HF0_UNCOMP 0 31*4882a593Smuzhiyun #define MASTER_CAMNOC_HF1_UNCOMP 1 32*4882a593Smuzhiyun #define MASTER_CAMNOC_SF_UNCOMP 2 33*4882a593Smuzhiyun #define SLAVE_CAMNOC_UNCOMP 3 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun #define MASTER_NPU 0 36*4882a593Smuzhiyun #define MASTER_NPU_PROC 1 37*4882a593Smuzhiyun #define SLAVE_CDSP_GEM_NOC 2 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun #define MASTER_SNOC_CNOC 0 40*4882a593Smuzhiyun #define MASTER_QDSS_DAP 1 41*4882a593Smuzhiyun #define SLAVE_A1NOC_CFG 2 42*4882a593Smuzhiyun #define SLAVE_A2NOC_CFG 3 43*4882a593Smuzhiyun #define SLAVE_AHB2PHY_SOUTH 4 44*4882a593Smuzhiyun #define SLAVE_AHB2PHY_CENTER 5 45*4882a593Smuzhiyun #define SLAVE_AOP 6 46*4882a593Smuzhiyun #define SLAVE_AOSS 7 47*4882a593Smuzhiyun #define SLAVE_BOOT_ROM 8 48*4882a593Smuzhiyun #define SLAVE_CAMERA_CFG 9 49*4882a593Smuzhiyun #define SLAVE_CAMERA_NRT_THROTTLE_CFG 10 50*4882a593Smuzhiyun #define SLAVE_CAMERA_RT_THROTTLE_CFG 11 51*4882a593Smuzhiyun #define SLAVE_CLK_CTL 12 52*4882a593Smuzhiyun #define SLAVE_RBCPR_CX_CFG 13 53*4882a593Smuzhiyun #define SLAVE_RBCPR_MX_CFG 14 54*4882a593Smuzhiyun #define SLAVE_CRYPTO_0_CFG 15 55*4882a593Smuzhiyun #define SLAVE_DCC_CFG 16 56*4882a593Smuzhiyun #define SLAVE_CNOC_DDRSS 17 57*4882a593Smuzhiyun #define SLAVE_DISPLAY_CFG 18 58*4882a593Smuzhiyun #define SLAVE_DISPLAY_RT_THROTTLE_CFG 19 59*4882a593Smuzhiyun #define SLAVE_DISPLAY_THROTTLE_CFG 20 60*4882a593Smuzhiyun #define SLAVE_EMMC_CFG 21 61*4882a593Smuzhiyun #define SLAVE_GLM 22 62*4882a593Smuzhiyun #define SLAVE_GFX3D_CFG 23 63*4882a593Smuzhiyun #define SLAVE_IMEM_CFG 24 64*4882a593Smuzhiyun #define SLAVE_IPA_CFG 25 65*4882a593Smuzhiyun #define SLAVE_CNOC_MNOC_CFG 26 66*4882a593Smuzhiyun #define SLAVE_CNOC_MSS 27 67*4882a593Smuzhiyun #define SLAVE_NPU_CFG 28 68*4882a593Smuzhiyun #define SLAVE_NPU_DMA_BWMON_CFG 29 69*4882a593Smuzhiyun #define SLAVE_NPU_PROC_BWMON_CFG 30 70*4882a593Smuzhiyun #define SLAVE_PDM 31 71*4882a593Smuzhiyun #define SLAVE_PIMEM_CFG 32 72*4882a593Smuzhiyun #define SLAVE_PRNG 33 73*4882a593Smuzhiyun #define SLAVE_QDSS_CFG 34 74*4882a593Smuzhiyun #define SLAVE_QM_CFG 35 75*4882a593Smuzhiyun #define SLAVE_QM_MPU_CFG 36 76*4882a593Smuzhiyun #define SLAVE_QSPI_0 37 77*4882a593Smuzhiyun #define SLAVE_QUP_0 38 78*4882a593Smuzhiyun #define SLAVE_QUP_1 39 79*4882a593Smuzhiyun #define SLAVE_SDCC_2 40 80*4882a593Smuzhiyun #define SLAVE_SECURITY 41 81*4882a593Smuzhiyun #define SLAVE_SNOC_CFG 42 82*4882a593Smuzhiyun #define SLAVE_TCSR 43 83*4882a593Smuzhiyun #define SLAVE_TLMM_WEST 44 84*4882a593Smuzhiyun #define SLAVE_TLMM_NORTH 45 85*4882a593Smuzhiyun #define SLAVE_TLMM_SOUTH 46 86*4882a593Smuzhiyun #define SLAVE_UFS_MEM_CFG 47 87*4882a593Smuzhiyun #define SLAVE_USB3 48 88*4882a593Smuzhiyun #define SLAVE_VENUS_CFG 49 89*4882a593Smuzhiyun #define SLAVE_VENUS_THROTTLE_CFG 50 90*4882a593Smuzhiyun #define SLAVE_VSENSE_CTRL_CFG 51 91*4882a593Smuzhiyun #define SLAVE_SERVICE_CNOC 52 92*4882a593Smuzhiyun 93*4882a593Smuzhiyun #define MASTER_CNOC_DC_NOC 0 94*4882a593Smuzhiyun #define SLAVE_GEM_NOC_CFG 1 95*4882a593Smuzhiyun #define SLAVE_LLCC_CFG 2 96*4882a593Smuzhiyun 97*4882a593Smuzhiyun #define MASTER_APPSS_PROC 0 98*4882a593Smuzhiyun #define MASTER_SYS_TCU 1 99*4882a593Smuzhiyun #define MASTER_GEM_NOC_CFG 2 100*4882a593Smuzhiyun #define MASTER_COMPUTE_NOC 3 101*4882a593Smuzhiyun #define MASTER_MNOC_HF_MEM_NOC 4 102*4882a593Smuzhiyun #define MASTER_MNOC_SF_MEM_NOC 5 103*4882a593Smuzhiyun #define MASTER_SNOC_GC_MEM_NOC 6 104*4882a593Smuzhiyun #define MASTER_SNOC_SF_MEM_NOC 7 105*4882a593Smuzhiyun #define MASTER_GFX3D 8 106*4882a593Smuzhiyun #define SLAVE_MSS_PROC_MS_MPU_CFG 9 107*4882a593Smuzhiyun #define SLAVE_GEM_NOC_SNOC 10 108*4882a593Smuzhiyun #define SLAVE_LLCC 11 109*4882a593Smuzhiyun #define SLAVE_SERVICE_GEM_NOC 12 110*4882a593Smuzhiyun 111*4882a593Smuzhiyun #define MASTER_IPA_CORE 0 112*4882a593Smuzhiyun #define SLAVE_IPA_CORE 1 113*4882a593Smuzhiyun 114*4882a593Smuzhiyun #define MASTER_LLCC 0 115*4882a593Smuzhiyun #define SLAVE_EBI1 1 116*4882a593Smuzhiyun 117*4882a593Smuzhiyun #define MASTER_CNOC_MNOC_CFG 0 118*4882a593Smuzhiyun #define MASTER_CAMNOC_HF0 1 119*4882a593Smuzhiyun #define MASTER_CAMNOC_HF1 2 120*4882a593Smuzhiyun #define MASTER_CAMNOC_SF 3 121*4882a593Smuzhiyun #define MASTER_MDP0 4 122*4882a593Smuzhiyun #define MASTER_ROTATOR 5 123*4882a593Smuzhiyun #define MASTER_VIDEO_P0 6 124*4882a593Smuzhiyun #define MASTER_VIDEO_PROC 7 125*4882a593Smuzhiyun #define SLAVE_MNOC_HF_MEM_NOC 8 126*4882a593Smuzhiyun #define SLAVE_MNOC_SF_MEM_NOC 9 127*4882a593Smuzhiyun #define SLAVE_SERVICE_MNOC 10 128*4882a593Smuzhiyun 129*4882a593Smuzhiyun #define MASTER_NPU_SYS 0 130*4882a593Smuzhiyun #define MASTER_NPU_NOC_CFG 1 131*4882a593Smuzhiyun #define SLAVE_NPU_CAL_DP0 2 132*4882a593Smuzhiyun #define SLAVE_NPU_CP 3 133*4882a593Smuzhiyun #define SLAVE_NPU_INT_DMA_BWMON_CFG 4 134*4882a593Smuzhiyun #define SLAVE_NPU_DPM 5 135*4882a593Smuzhiyun #define SLAVE_ISENSE_CFG 6 136*4882a593Smuzhiyun #define SLAVE_NPU_LLM_CFG 7 137*4882a593Smuzhiyun #define SLAVE_NPU_TCM 8 138*4882a593Smuzhiyun #define SLAVE_NPU_COMPUTE_NOC 9 139*4882a593Smuzhiyun #define SLAVE_SERVICE_NPU_NOC 10 140*4882a593Smuzhiyun 141*4882a593Smuzhiyun #define MASTER_QUP_CORE_0 0 142*4882a593Smuzhiyun #define MASTER_QUP_CORE_1 1 143*4882a593Smuzhiyun #define SLAVE_QUP_CORE_0 2 144*4882a593Smuzhiyun #define SLAVE_QUP_CORE_1 3 145*4882a593Smuzhiyun 146*4882a593Smuzhiyun #define MASTER_SNOC_CFG 0 147*4882a593Smuzhiyun #define MASTER_A1NOC_SNOC 1 148*4882a593Smuzhiyun #define MASTER_A2NOC_SNOC 2 149*4882a593Smuzhiyun #define MASTER_GEM_NOC_SNOC 3 150*4882a593Smuzhiyun #define MASTER_PIMEM 4 151*4882a593Smuzhiyun #define SLAVE_APPSS 5 152*4882a593Smuzhiyun #define SLAVE_SNOC_CNOC 6 153*4882a593Smuzhiyun #define SLAVE_SNOC_GEM_NOC_GC 7 154*4882a593Smuzhiyun #define SLAVE_SNOC_GEM_NOC_SF 8 155*4882a593Smuzhiyun #define SLAVE_IMEM 9 156*4882a593Smuzhiyun #define SLAVE_PIMEM 10 157*4882a593Smuzhiyun #define SLAVE_SERVICE_SNOC 11 158*4882a593Smuzhiyun #define SLAVE_QDSS_STM 12 159*4882a593Smuzhiyun #define SLAVE_TCU 13 160*4882a593Smuzhiyun 161*4882a593Smuzhiyun #endif 162