1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Qualcomm interconnect IDs 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (c) 2019, Linaro Ltd. 6*4882a593Smuzhiyun * Author: Georgi Djakov <georgi.djakov@linaro.org> 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #ifndef __DT_BINDINGS_INTERCONNECT_QCOM_QCS404_H 10*4882a593Smuzhiyun #define __DT_BINDINGS_INTERCONNECT_QCOM_QCS404_H 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #define MASTER_AMPSS_M0 0 13*4882a593Smuzhiyun #define MASTER_OXILI 1 14*4882a593Smuzhiyun #define MASTER_MDP_PORT0 2 15*4882a593Smuzhiyun #define MASTER_SNOC_BIMC_1 3 16*4882a593Smuzhiyun #define MASTER_TCU_0 4 17*4882a593Smuzhiyun #define SLAVE_EBI_CH0 5 18*4882a593Smuzhiyun #define SLAVE_BIMC_SNOC 6 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun #define MASTER_SPDM 0 21*4882a593Smuzhiyun #define MASTER_BLSP_1 1 22*4882a593Smuzhiyun #define MASTER_BLSP_2 2 23*4882a593Smuzhiyun #define MASTER_XI_USB_HS1 3 24*4882a593Smuzhiyun #define MASTER_CRYPT0 4 25*4882a593Smuzhiyun #define MASTER_SDCC_1 5 26*4882a593Smuzhiyun #define MASTER_SDCC_2 6 27*4882a593Smuzhiyun #define MASTER_SNOC_PCNOC 7 28*4882a593Smuzhiyun #define MASTER_QPIC 8 29*4882a593Smuzhiyun #define PCNOC_INT_0 9 30*4882a593Smuzhiyun #define PCNOC_INT_2 10 31*4882a593Smuzhiyun #define PCNOC_INT_3 11 32*4882a593Smuzhiyun #define PCNOC_S_0 12 33*4882a593Smuzhiyun #define PCNOC_S_1 13 34*4882a593Smuzhiyun #define PCNOC_S_2 14 35*4882a593Smuzhiyun #define PCNOC_S_3 15 36*4882a593Smuzhiyun #define PCNOC_S_4 16 37*4882a593Smuzhiyun #define PCNOC_S_6 17 38*4882a593Smuzhiyun #define PCNOC_S_7 18 39*4882a593Smuzhiyun #define PCNOC_S_8 19 40*4882a593Smuzhiyun #define PCNOC_S_9 20 41*4882a593Smuzhiyun #define PCNOC_S_10 21 42*4882a593Smuzhiyun #define PCNOC_S_11 22 43*4882a593Smuzhiyun #define SLAVE_SPDM 23 44*4882a593Smuzhiyun #define SLAVE_PDM 24 45*4882a593Smuzhiyun #define SLAVE_PRNG 25 46*4882a593Smuzhiyun #define SLAVE_TCSR 26 47*4882a593Smuzhiyun #define SLAVE_SNOC_CFG 27 48*4882a593Smuzhiyun #define SLAVE_MESSAGE_RAM 28 49*4882a593Smuzhiyun #define SLAVE_DISP_SS_CFG 29 50*4882a593Smuzhiyun #define SLAVE_GPU_CFG 30 51*4882a593Smuzhiyun #define SLAVE_BLSP_1 31 52*4882a593Smuzhiyun #define SLAVE_BLSP_2 32 53*4882a593Smuzhiyun #define SLAVE_TLMM_NORTH 33 54*4882a593Smuzhiyun #define SLAVE_PCIE 34 55*4882a593Smuzhiyun #define SLAVE_ETHERNET 35 56*4882a593Smuzhiyun #define SLAVE_TLMM_EAST 36 57*4882a593Smuzhiyun #define SLAVE_TCU 37 58*4882a593Smuzhiyun #define SLAVE_PMIC_ARB 38 59*4882a593Smuzhiyun #define SLAVE_SDCC_1 39 60*4882a593Smuzhiyun #define SLAVE_SDCC_2 40 61*4882a593Smuzhiyun #define SLAVE_TLMM_SOUTH 41 62*4882a593Smuzhiyun #define SLAVE_USB_HS 42 63*4882a593Smuzhiyun #define SLAVE_USB3 43 64*4882a593Smuzhiyun #define SLAVE_CRYPTO_0_CFG 44 65*4882a593Smuzhiyun #define SLAVE_PCNOC_SNOC 45 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun #define MASTER_QDSS_BAM 0 68*4882a593Smuzhiyun #define MASTER_BIMC_SNOC 1 69*4882a593Smuzhiyun #define MASTER_PCNOC_SNOC 2 70*4882a593Smuzhiyun #define MASTER_QDSS_ETR 3 71*4882a593Smuzhiyun #define MASTER_EMAC 4 72*4882a593Smuzhiyun #define MASTER_PCIE 5 73*4882a593Smuzhiyun #define MASTER_USB3 6 74*4882a593Smuzhiyun #define QDSS_INT 7 75*4882a593Smuzhiyun #define SNOC_INT_0 8 76*4882a593Smuzhiyun #define SNOC_INT_1 9 77*4882a593Smuzhiyun #define SNOC_INT_2 10 78*4882a593Smuzhiyun #define SLAVE_KPSS_AHB 11 79*4882a593Smuzhiyun #define SLAVE_WCSS 12 80*4882a593Smuzhiyun #define SLAVE_SNOC_BIMC_1 13 81*4882a593Smuzhiyun #define SLAVE_IMEM 14 82*4882a593Smuzhiyun #define SLAVE_SNOC_PCNOC 15 83*4882a593Smuzhiyun #define SLAVE_QDSS_STM 16 84*4882a593Smuzhiyun #define SLAVE_CATS_0 17 85*4882a593Smuzhiyun #define SLAVE_CATS_1 18 86*4882a593Smuzhiyun #define SLAVE_LPASS 19 87*4882a593Smuzhiyun 88*4882a593Smuzhiyun #endif 89