1*4882a593Smuzhiyun /* SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Qualcomm msm8974 interconnect IDs 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (c) 2019 Brian Masney <masneyb@onstation.org> 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #ifndef __DT_BINDINGS_INTERCONNECT_QCOM_MSM8974_H 9*4882a593Smuzhiyun #define __DT_BINDINGS_INTERCONNECT_QCOM_MSM8974_H 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #define BIMC_MAS_AMPSS_M0 0 12*4882a593Smuzhiyun #define BIMC_MAS_AMPSS_M1 1 13*4882a593Smuzhiyun #define BIMC_MAS_MSS_PROC 2 14*4882a593Smuzhiyun #define BIMC_TO_MNOC 3 15*4882a593Smuzhiyun #define BIMC_TO_SNOC 4 16*4882a593Smuzhiyun #define BIMC_SLV_EBI_CH0 5 17*4882a593Smuzhiyun #define BIMC_SLV_AMPSS_L2 6 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun #define CNOC_MAS_RPM_INST 0 20*4882a593Smuzhiyun #define CNOC_MAS_RPM_DATA 1 21*4882a593Smuzhiyun #define CNOC_MAS_RPM_SYS 2 22*4882a593Smuzhiyun #define CNOC_MAS_DEHR 3 23*4882a593Smuzhiyun #define CNOC_MAS_QDSS_DAP 4 24*4882a593Smuzhiyun #define CNOC_MAS_SPDM 5 25*4882a593Smuzhiyun #define CNOC_MAS_TIC 6 26*4882a593Smuzhiyun #define CNOC_SLV_CLK_CTL 7 27*4882a593Smuzhiyun #define CNOC_SLV_CNOC_MSS 8 28*4882a593Smuzhiyun #define CNOC_SLV_SECURITY 9 29*4882a593Smuzhiyun #define CNOC_SLV_TCSR 10 30*4882a593Smuzhiyun #define CNOC_SLV_TLMM 11 31*4882a593Smuzhiyun #define CNOC_SLV_CRYPTO_0_CFG 12 32*4882a593Smuzhiyun #define CNOC_SLV_CRYPTO_1_CFG 13 33*4882a593Smuzhiyun #define CNOC_SLV_IMEM_CFG 14 34*4882a593Smuzhiyun #define CNOC_SLV_MESSAGE_RAM 15 35*4882a593Smuzhiyun #define CNOC_SLV_BIMC_CFG 16 36*4882a593Smuzhiyun #define CNOC_SLV_BOOT_ROM 17 37*4882a593Smuzhiyun #define CNOC_SLV_PMIC_ARB 18 38*4882a593Smuzhiyun #define CNOC_SLV_SPDM_WRAPPER 19 39*4882a593Smuzhiyun #define CNOC_SLV_DEHR_CFG 20 40*4882a593Smuzhiyun #define CNOC_SLV_MPM 21 41*4882a593Smuzhiyun #define CNOC_SLV_QDSS_CFG 22 42*4882a593Smuzhiyun #define CNOC_SLV_RBCPR_CFG 23 43*4882a593Smuzhiyun #define CNOC_SLV_RBCPR_QDSS_APU_CFG 24 44*4882a593Smuzhiyun #define CNOC_TO_SNOC 25 45*4882a593Smuzhiyun #define CNOC_SLV_CNOC_ONOC_CFG 26 46*4882a593Smuzhiyun #define CNOC_SLV_CNOC_MNOC_MMSS_CFG 27 47*4882a593Smuzhiyun #define CNOC_SLV_CNOC_MNOC_CFG 28 48*4882a593Smuzhiyun #define CNOC_SLV_PNOC_CFG 29 49*4882a593Smuzhiyun #define CNOC_SLV_SNOC_MPU_CFG 30 50*4882a593Smuzhiyun #define CNOC_SLV_SNOC_CFG 31 51*4882a593Smuzhiyun #define CNOC_SLV_EBI1_DLL_CFG 32 52*4882a593Smuzhiyun #define CNOC_SLV_PHY_APU_CFG 33 53*4882a593Smuzhiyun #define CNOC_SLV_EBI1_PHY_CFG 34 54*4882a593Smuzhiyun #define CNOC_SLV_RPM 35 55*4882a593Smuzhiyun #define CNOC_SLV_SERVICE_CNOC 36 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun #define MNOC_MAS_GRAPHICS_3D 0 58*4882a593Smuzhiyun #define MNOC_MAS_JPEG 1 59*4882a593Smuzhiyun #define MNOC_MAS_MDP_PORT0 2 60*4882a593Smuzhiyun #define MNOC_MAS_VIDEO_P0 3 61*4882a593Smuzhiyun #define MNOC_MAS_VIDEO_P1 4 62*4882a593Smuzhiyun #define MNOC_MAS_VFE 5 63*4882a593Smuzhiyun #define MNOC_TO_CNOC 6 64*4882a593Smuzhiyun #define MNOC_TO_BIMC 7 65*4882a593Smuzhiyun #define MNOC_SLV_CAMERA_CFG 8 66*4882a593Smuzhiyun #define MNOC_SLV_DISPLAY_CFG 9 67*4882a593Smuzhiyun #define MNOC_SLV_OCMEM_CFG 10 68*4882a593Smuzhiyun #define MNOC_SLV_CPR_CFG 11 69*4882a593Smuzhiyun #define MNOC_SLV_CPR_XPU_CFG 12 70*4882a593Smuzhiyun #define MNOC_SLV_MISC_CFG 13 71*4882a593Smuzhiyun #define MNOC_SLV_MISC_XPU_CFG 14 72*4882a593Smuzhiyun #define MNOC_SLV_VENUS_CFG 15 73*4882a593Smuzhiyun #define MNOC_SLV_GRAPHICS_3D_CFG 16 74*4882a593Smuzhiyun #define MNOC_SLV_MMSS_CLK_CFG 17 75*4882a593Smuzhiyun #define MNOC_SLV_MMSS_CLK_XPU_CFG 18 76*4882a593Smuzhiyun #define MNOC_SLV_MNOC_MPU_CFG 19 77*4882a593Smuzhiyun #define MNOC_SLV_ONOC_MPU_CFG 20 78*4882a593Smuzhiyun #define MNOC_SLV_SERVICE_MNOC 21 79*4882a593Smuzhiyun 80*4882a593Smuzhiyun #define OCMEM_NOC_TO_OCMEM_VNOC 0 81*4882a593Smuzhiyun #define OCMEM_MAS_JPEG_OCMEM 1 82*4882a593Smuzhiyun #define OCMEM_MAS_MDP_OCMEM 2 83*4882a593Smuzhiyun #define OCMEM_MAS_VIDEO_P0_OCMEM 3 84*4882a593Smuzhiyun #define OCMEM_MAS_VIDEO_P1_OCMEM 4 85*4882a593Smuzhiyun #define OCMEM_MAS_VFE_OCMEM 5 86*4882a593Smuzhiyun #define OCMEM_MAS_CNOC_ONOC_CFG 6 87*4882a593Smuzhiyun #define OCMEM_SLV_SERVICE_ONOC 7 88*4882a593Smuzhiyun #define OCMEM_VNOC_TO_SNOC 8 89*4882a593Smuzhiyun #define OCMEM_VNOC_TO_OCMEM_NOC 9 90*4882a593Smuzhiyun #define OCMEM_VNOC_MAS_GFX3D 10 91*4882a593Smuzhiyun #define OCMEM_SLV_OCMEM 11 92*4882a593Smuzhiyun 93*4882a593Smuzhiyun #define PNOC_MAS_PNOC_CFG 0 94*4882a593Smuzhiyun #define PNOC_MAS_SDCC_1 1 95*4882a593Smuzhiyun #define PNOC_MAS_SDCC_3 2 96*4882a593Smuzhiyun #define PNOC_MAS_SDCC_4 3 97*4882a593Smuzhiyun #define PNOC_MAS_SDCC_2 4 98*4882a593Smuzhiyun #define PNOC_MAS_TSIF 5 99*4882a593Smuzhiyun #define PNOC_MAS_BAM_DMA 6 100*4882a593Smuzhiyun #define PNOC_MAS_BLSP_2 7 101*4882a593Smuzhiyun #define PNOC_MAS_USB_HSIC 8 102*4882a593Smuzhiyun #define PNOC_MAS_BLSP_1 9 103*4882a593Smuzhiyun #define PNOC_MAS_USB_HS 10 104*4882a593Smuzhiyun #define PNOC_TO_SNOC 11 105*4882a593Smuzhiyun #define PNOC_SLV_SDCC_1 12 106*4882a593Smuzhiyun #define PNOC_SLV_SDCC_3 13 107*4882a593Smuzhiyun #define PNOC_SLV_SDCC_2 14 108*4882a593Smuzhiyun #define PNOC_SLV_SDCC_4 15 109*4882a593Smuzhiyun #define PNOC_SLV_TSIF 16 110*4882a593Smuzhiyun #define PNOC_SLV_BAM_DMA 17 111*4882a593Smuzhiyun #define PNOC_SLV_BLSP_2 18 112*4882a593Smuzhiyun #define PNOC_SLV_USB_HSIC 19 113*4882a593Smuzhiyun #define PNOC_SLV_BLSP_1 20 114*4882a593Smuzhiyun #define PNOC_SLV_USB_HS 21 115*4882a593Smuzhiyun #define PNOC_SLV_PDM 22 116*4882a593Smuzhiyun #define PNOC_SLV_PERIPH_APU_CFG 23 117*4882a593Smuzhiyun #define PNOC_SLV_PNOC_MPU_CFG 24 118*4882a593Smuzhiyun #define PNOC_SLV_PRNG 25 119*4882a593Smuzhiyun #define PNOC_SLV_SERVICE_PNOC 26 120*4882a593Smuzhiyun 121*4882a593Smuzhiyun #define SNOC_MAS_LPASS_AHB 0 122*4882a593Smuzhiyun #define SNOC_MAS_QDSS_BAM 1 123*4882a593Smuzhiyun #define SNOC_MAS_SNOC_CFG 2 124*4882a593Smuzhiyun #define SNOC_TO_BIMC 3 125*4882a593Smuzhiyun #define SNOC_TO_CNOC 4 126*4882a593Smuzhiyun #define SNOC_TO_PNOC 5 127*4882a593Smuzhiyun #define SNOC_TO_OCMEM_VNOC 6 128*4882a593Smuzhiyun #define SNOC_MAS_CRYPTO_CORE0 7 129*4882a593Smuzhiyun #define SNOC_MAS_CRYPTO_CORE1 8 130*4882a593Smuzhiyun #define SNOC_MAS_LPASS_PROC 9 131*4882a593Smuzhiyun #define SNOC_MAS_MSS 10 132*4882a593Smuzhiyun #define SNOC_MAS_MSS_NAV 11 133*4882a593Smuzhiyun #define SNOC_MAS_OCMEM_DMA 12 134*4882a593Smuzhiyun #define SNOC_MAS_WCSS 13 135*4882a593Smuzhiyun #define SNOC_MAS_QDSS_ETR 14 136*4882a593Smuzhiyun #define SNOC_MAS_USB3 15 137*4882a593Smuzhiyun #define SNOC_SLV_AMPSS 16 138*4882a593Smuzhiyun #define SNOC_SLV_LPASS 17 139*4882a593Smuzhiyun #define SNOC_SLV_USB3 18 140*4882a593Smuzhiyun #define SNOC_SLV_WCSS 19 141*4882a593Smuzhiyun #define SNOC_SLV_OCIMEM 20 142*4882a593Smuzhiyun #define SNOC_SLV_SNOC_OCMEM 21 143*4882a593Smuzhiyun #define SNOC_SLV_SERVICE_SNOC 22 144*4882a593Smuzhiyun #define SNOC_SLV_QDSS_STM 23 145*4882a593Smuzhiyun 146*4882a593Smuzhiyun #endif 147