1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Qualcomm interconnect IDs 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (c) 2019, Linaro Ltd. 6*4882a593Smuzhiyun * Author: Georgi Djakov <georgi.djakov@linaro.org> 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #ifndef __DT_BINDINGS_INTERCONNECT_QCOM_MSM8916_H 10*4882a593Smuzhiyun #define __DT_BINDINGS_INTERCONNECT_QCOM_MSM8916_H 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #define BIMC_SNOC_SLV 0 13*4882a593Smuzhiyun #define MASTER_JPEG 1 14*4882a593Smuzhiyun #define MASTER_MDP_PORT0 2 15*4882a593Smuzhiyun #define MASTER_QDSS_BAM 3 16*4882a593Smuzhiyun #define MASTER_QDSS_ETR 4 17*4882a593Smuzhiyun #define MASTER_SNOC_CFG 5 18*4882a593Smuzhiyun #define MASTER_VFE 6 19*4882a593Smuzhiyun #define MASTER_VIDEO_P0 7 20*4882a593Smuzhiyun #define SNOC_MM_INT_0 8 21*4882a593Smuzhiyun #define SNOC_MM_INT_1 9 22*4882a593Smuzhiyun #define SNOC_MM_INT_2 10 23*4882a593Smuzhiyun #define SNOC_MM_INT_BIMC 11 24*4882a593Smuzhiyun #define PCNOC_SNOC_SLV 12 25*4882a593Smuzhiyun #define SLAVE_APSS 13 26*4882a593Smuzhiyun #define SLAVE_CATS_128 14 27*4882a593Smuzhiyun #define SLAVE_OCMEM_64 15 28*4882a593Smuzhiyun #define SLAVE_IMEM 16 29*4882a593Smuzhiyun #define SLAVE_QDSS_STM 17 30*4882a593Smuzhiyun #define SLAVE_SRVC_SNOC 18 31*4882a593Smuzhiyun #define SNOC_BIMC_0_MAS 19 32*4882a593Smuzhiyun #define SNOC_BIMC_1_MAS 20 33*4882a593Smuzhiyun #define SNOC_INT_0 21 34*4882a593Smuzhiyun #define SNOC_INT_1 22 35*4882a593Smuzhiyun #define SNOC_INT_BIMC 23 36*4882a593Smuzhiyun #define SNOC_PCNOC_MAS 24 37*4882a593Smuzhiyun #define SNOC_QDSS_INT 25 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun #define BIMC_SNOC_MAS 0 40*4882a593Smuzhiyun #define MASTER_AMPSS_M0 1 41*4882a593Smuzhiyun #define MASTER_GRAPHICS_3D 2 42*4882a593Smuzhiyun #define MASTER_TCU0 3 43*4882a593Smuzhiyun #define MASTER_TCU1 4 44*4882a593Smuzhiyun #define SLAVE_AMPSS_L2 5 45*4882a593Smuzhiyun #define SLAVE_EBI_CH0 6 46*4882a593Smuzhiyun #define SNOC_BIMC_0_SLV 7 47*4882a593Smuzhiyun #define SNOC_BIMC_1_SLV 8 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun #define MASTER_BLSP_1 0 50*4882a593Smuzhiyun #define MASTER_DEHR 1 51*4882a593Smuzhiyun #define MASTER_LPASS 2 52*4882a593Smuzhiyun #define MASTER_CRYPTO_CORE0 3 53*4882a593Smuzhiyun #define MASTER_SDCC_1 4 54*4882a593Smuzhiyun #define MASTER_SDCC_2 5 55*4882a593Smuzhiyun #define MASTER_SPDM 6 56*4882a593Smuzhiyun #define MASTER_USB_HS 7 57*4882a593Smuzhiyun #define PCNOC_INT_0 8 58*4882a593Smuzhiyun #define PCNOC_INT_1 9 59*4882a593Smuzhiyun #define PCNOC_MAS_0 10 60*4882a593Smuzhiyun #define PCNOC_MAS_1 11 61*4882a593Smuzhiyun #define PCNOC_SLV_0 12 62*4882a593Smuzhiyun #define PCNOC_SLV_1 13 63*4882a593Smuzhiyun #define PCNOC_SLV_2 14 64*4882a593Smuzhiyun #define PCNOC_SLV_3 15 65*4882a593Smuzhiyun #define PCNOC_SLV_4 16 66*4882a593Smuzhiyun #define PCNOC_SLV_8 17 67*4882a593Smuzhiyun #define PCNOC_SLV_9 18 68*4882a593Smuzhiyun #define PCNOC_SNOC_MAS 19 69*4882a593Smuzhiyun #define SLAVE_BIMC_CFG 20 70*4882a593Smuzhiyun #define SLAVE_BLSP_1 21 71*4882a593Smuzhiyun #define SLAVE_BOOT_ROM 22 72*4882a593Smuzhiyun #define SLAVE_CAMERA_CFG 23 73*4882a593Smuzhiyun #define SLAVE_CLK_CTL 24 74*4882a593Smuzhiyun #define SLAVE_CRYPTO_0_CFG 25 75*4882a593Smuzhiyun #define SLAVE_DEHR_CFG 26 76*4882a593Smuzhiyun #define SLAVE_DISPLAY_CFG 27 77*4882a593Smuzhiyun #define SLAVE_GRAPHICS_3D_CFG 28 78*4882a593Smuzhiyun #define SLAVE_IMEM_CFG 29 79*4882a593Smuzhiyun #define SLAVE_LPASS 30 80*4882a593Smuzhiyun #define SLAVE_MPM 31 81*4882a593Smuzhiyun #define SLAVE_MSG_RAM 32 82*4882a593Smuzhiyun #define SLAVE_MSS 33 83*4882a593Smuzhiyun #define SLAVE_PDM 34 84*4882a593Smuzhiyun #define SLAVE_PMIC_ARB 35 85*4882a593Smuzhiyun #define SLAVE_PCNOC_CFG 36 86*4882a593Smuzhiyun #define SLAVE_PRNG 37 87*4882a593Smuzhiyun #define SLAVE_QDSS_CFG 38 88*4882a593Smuzhiyun #define SLAVE_RBCPR_CFG 39 89*4882a593Smuzhiyun #define SLAVE_SDCC_1 40 90*4882a593Smuzhiyun #define SLAVE_SDCC_2 41 91*4882a593Smuzhiyun #define SLAVE_SECURITY 42 92*4882a593Smuzhiyun #define SLAVE_SNOC_CFG 43 93*4882a593Smuzhiyun #define SLAVE_SPDM 44 94*4882a593Smuzhiyun #define SLAVE_TCSR 45 95*4882a593Smuzhiyun #define SLAVE_TLMM 46 96*4882a593Smuzhiyun #define SLAVE_USB_HS 47 97*4882a593Smuzhiyun #define SLAVE_VENUS_CFG 48 98*4882a593Smuzhiyun #define SNOC_PCNOC_SLV 49 99*4882a593Smuzhiyun 100*4882a593Smuzhiyun #endif 101