xref: /OK3568_Linux_fs/kernel/include/dt-bindings/interconnect/qcom,sm8150.h (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * Qualcomm SM8150 interconnect IDs
4*4882a593Smuzhiyun  *
5*4882a593Smuzhiyun  * Copyright (c) 2020, The Linux Foundation. All rights reserved.
6*4882a593Smuzhiyun  */
7*4882a593Smuzhiyun 
8*4882a593Smuzhiyun #ifndef __DT_BINDINGS_INTERCONNECT_QCOM_SM8150_H
9*4882a593Smuzhiyun #define __DT_BINDINGS_INTERCONNECT_QCOM_SM8150_H
10*4882a593Smuzhiyun 
11*4882a593Smuzhiyun #define MASTER_A1NOC_CFG		0
12*4882a593Smuzhiyun #define MASTER_QUP_0			1
13*4882a593Smuzhiyun #define MASTER_EMAC			2
14*4882a593Smuzhiyun #define MASTER_UFS_MEM			3
15*4882a593Smuzhiyun #define MASTER_USB3			4
16*4882a593Smuzhiyun #define MASTER_USB3_1			5
17*4882a593Smuzhiyun #define A1NOC_SNOC_SLV			6
18*4882a593Smuzhiyun #define SLAVE_SERVICE_A1NOC		7
19*4882a593Smuzhiyun 
20*4882a593Smuzhiyun #define MASTER_A2NOC_CFG		0
21*4882a593Smuzhiyun #define MASTER_QDSS_BAM			1
22*4882a593Smuzhiyun #define MASTER_QSPI			2
23*4882a593Smuzhiyun #define MASTER_QUP_1			3
24*4882a593Smuzhiyun #define MASTER_QUP_2			4
25*4882a593Smuzhiyun #define MASTER_SENSORS_AHB		5
26*4882a593Smuzhiyun #define MASTER_TSIF			6
27*4882a593Smuzhiyun #define MASTER_CNOC_A2NOC		7
28*4882a593Smuzhiyun #define MASTER_CRYPTO_CORE_0		8
29*4882a593Smuzhiyun #define MASTER_IPA			9
30*4882a593Smuzhiyun #define MASTER_PCIE			10
31*4882a593Smuzhiyun #define MASTER_PCIE_1			11
32*4882a593Smuzhiyun #define MASTER_QDSS_ETR			12
33*4882a593Smuzhiyun #define MASTER_SDCC_2			13
34*4882a593Smuzhiyun #define MASTER_SDCC_4			14
35*4882a593Smuzhiyun #define A2NOC_SNOC_SLV			15
36*4882a593Smuzhiyun #define SLAVE_ANOC_PCIE_GEM_NOC		16
37*4882a593Smuzhiyun #define SLAVE_SERVICE_A2NOC		17
38*4882a593Smuzhiyun 
39*4882a593Smuzhiyun #define MASTER_CAMNOC_HF0_UNCOMP	0
40*4882a593Smuzhiyun #define MASTER_CAMNOC_HF1_UNCOMP	1
41*4882a593Smuzhiyun #define MASTER_CAMNOC_SF_UNCOMP		2
42*4882a593Smuzhiyun #define SLAVE_CAMNOC_UNCOMP		3
43*4882a593Smuzhiyun 
44*4882a593Smuzhiyun #define MASTER_NPU			0
45*4882a593Smuzhiyun #define SLAVE_CDSP_MEM_NOC		1
46*4882a593Smuzhiyun 
47*4882a593Smuzhiyun #define MASTER_SPDM			0
48*4882a593Smuzhiyun #define SNOC_CNOC_MAS			1
49*4882a593Smuzhiyun #define MASTER_QDSS_DAP			2
50*4882a593Smuzhiyun #define SLAVE_A1NOC_CFG			3
51*4882a593Smuzhiyun #define SLAVE_A2NOC_CFG			4
52*4882a593Smuzhiyun #define SLAVE_AHB2PHY_SOUTH		5
53*4882a593Smuzhiyun #define SLAVE_AOP			6
54*4882a593Smuzhiyun #define SLAVE_AOSS			7
55*4882a593Smuzhiyun #define SLAVE_CAMERA_CFG		8
56*4882a593Smuzhiyun #define SLAVE_CLK_CTL			9
57*4882a593Smuzhiyun #define SLAVE_CDSP_CFG			10
58*4882a593Smuzhiyun #define SLAVE_RBCPR_CX_CFG		11
59*4882a593Smuzhiyun #define SLAVE_RBCPR_MMCX_CFG		12
60*4882a593Smuzhiyun #define SLAVE_RBCPR_MX_CFG		13
61*4882a593Smuzhiyun #define SLAVE_CRYPTO_0_CFG		14
62*4882a593Smuzhiyun #define SLAVE_CNOC_DDRSS		15
63*4882a593Smuzhiyun #define SLAVE_DISPLAY_CFG		16
64*4882a593Smuzhiyun #define SLAVE_EMAC_CFG			17
65*4882a593Smuzhiyun #define SLAVE_GLM			18
66*4882a593Smuzhiyun #define SLAVE_GRAPHICS_3D_CFG		19
67*4882a593Smuzhiyun #define SLAVE_IMEM_CFG			20
68*4882a593Smuzhiyun #define SLAVE_IPA_CFG			21
69*4882a593Smuzhiyun #define SLAVE_CNOC_MNOC_CFG		22
70*4882a593Smuzhiyun #define SLAVE_NPU_CFG			23
71*4882a593Smuzhiyun #define SLAVE_PCIE_0_CFG		24
72*4882a593Smuzhiyun #define SLAVE_PCIE_1_CFG		25
73*4882a593Smuzhiyun #define SLAVE_NORTH_PHY_CFG		26
74*4882a593Smuzhiyun #define SLAVE_PIMEM_CFG			27
75*4882a593Smuzhiyun #define SLAVE_PRNG			28
76*4882a593Smuzhiyun #define SLAVE_QDSS_CFG			29
77*4882a593Smuzhiyun #define SLAVE_QSPI			30
78*4882a593Smuzhiyun #define SLAVE_QUP_2			31
79*4882a593Smuzhiyun #define SLAVE_QUP_1			32
80*4882a593Smuzhiyun #define SLAVE_QUP_0			33
81*4882a593Smuzhiyun #define SLAVE_SDCC_2			34
82*4882a593Smuzhiyun #define SLAVE_SDCC_4			35
83*4882a593Smuzhiyun #define SLAVE_SNOC_CFG			36
84*4882a593Smuzhiyun #define SLAVE_SPDM_WRAPPER		37
85*4882a593Smuzhiyun #define SLAVE_SPSS_CFG			38
86*4882a593Smuzhiyun #define SLAVE_SSC_CFG			39
87*4882a593Smuzhiyun #define SLAVE_TCSR			40
88*4882a593Smuzhiyun #define SLAVE_TLMM_EAST			41
89*4882a593Smuzhiyun #define SLAVE_TLMM_NORTH		42
90*4882a593Smuzhiyun #define SLAVE_TLMM_SOUTH		43
91*4882a593Smuzhiyun #define SLAVE_TLMM_WEST			44
92*4882a593Smuzhiyun #define SLAVE_TSIF			45
93*4882a593Smuzhiyun #define SLAVE_UFS_CARD_CFG		46
94*4882a593Smuzhiyun #define SLAVE_UFS_MEM_CFG		47
95*4882a593Smuzhiyun #define SLAVE_USB3			48
96*4882a593Smuzhiyun #define SLAVE_USB3_1			49
97*4882a593Smuzhiyun #define SLAVE_VENUS_CFG			50
98*4882a593Smuzhiyun #define SLAVE_VSENSE_CTRL_CFG		51
99*4882a593Smuzhiyun #define SLAVE_CNOC_A2NOC		52
100*4882a593Smuzhiyun #define SLAVE_SERVICE_CNOC		53
101*4882a593Smuzhiyun 
102*4882a593Smuzhiyun #define MASTER_CNOC_DC_NOC		0
103*4882a593Smuzhiyun #define SLAVE_LLCC_CFG			1
104*4882a593Smuzhiyun #define SLAVE_GEM_NOC_CFG		2
105*4882a593Smuzhiyun 
106*4882a593Smuzhiyun #define MASTER_AMPSS_M0			0
107*4882a593Smuzhiyun #define MASTER_GPU_TCU			1
108*4882a593Smuzhiyun #define MASTER_SYS_TCU			2
109*4882a593Smuzhiyun #define MASTER_GEM_NOC_CFG		3
110*4882a593Smuzhiyun #define MASTER_COMPUTE_NOC		4
111*4882a593Smuzhiyun #define MASTER_GRAPHICS_3D		5
112*4882a593Smuzhiyun #define MASTER_MNOC_HF_MEM_NOC		6
113*4882a593Smuzhiyun #define MASTER_MNOC_SF_MEM_NOC		7
114*4882a593Smuzhiyun #define MASTER_GEM_NOC_PCIE_SNOC	8
115*4882a593Smuzhiyun #define MASTER_SNOC_GC_MEM_NOC		9
116*4882a593Smuzhiyun #define MASTER_SNOC_SF_MEM_NOC		10
117*4882a593Smuzhiyun #define MASTER_ECC			11
118*4882a593Smuzhiyun #define SLAVE_MSS_PROC_MS_MPU_CFG	12
119*4882a593Smuzhiyun #define SLAVE_ECC			13
120*4882a593Smuzhiyun #define SLAVE_GEM_NOC_SNOC		14
121*4882a593Smuzhiyun #define SLAVE_LLCC			15
122*4882a593Smuzhiyun #define SLAVE_SERVICE_GEM_NOC		16
123*4882a593Smuzhiyun 
124*4882a593Smuzhiyun #define MASTER_IPA_CORE			0
125*4882a593Smuzhiyun #define SLAVE_IPA_CORE			1
126*4882a593Smuzhiyun 
127*4882a593Smuzhiyun #define MASTER_LLCC			0
128*4882a593Smuzhiyun #define SLAVE_EBI_CH0			1
129*4882a593Smuzhiyun 
130*4882a593Smuzhiyun #define MASTER_CNOC_MNOC_CFG		0
131*4882a593Smuzhiyun #define MASTER_CAMNOC_HF0		1
132*4882a593Smuzhiyun #define MASTER_CAMNOC_HF1		2
133*4882a593Smuzhiyun #define MASTER_CAMNOC_SF		3
134*4882a593Smuzhiyun #define MASTER_MDP_PORT0		4
135*4882a593Smuzhiyun #define MASTER_MDP_PORT1		5
136*4882a593Smuzhiyun #define MASTER_ROTATOR			6
137*4882a593Smuzhiyun #define MASTER_VIDEO_P0			7
138*4882a593Smuzhiyun #define MASTER_VIDEO_P1			8
139*4882a593Smuzhiyun #define MASTER_VIDEO_PROC		9
140*4882a593Smuzhiyun #define SLAVE_MNOC_SF_MEM_NOC		10
141*4882a593Smuzhiyun #define SLAVE_MNOC_HF_MEM_NOC		11
142*4882a593Smuzhiyun #define SLAVE_SERVICE_MNOC		12
143*4882a593Smuzhiyun 
144*4882a593Smuzhiyun #define MASTER_SNOC_CFG			0
145*4882a593Smuzhiyun #define A1NOC_SNOC_MAS			1
146*4882a593Smuzhiyun #define A2NOC_SNOC_MAS			2
147*4882a593Smuzhiyun #define MASTER_GEM_NOC_SNOC		3
148*4882a593Smuzhiyun #define MASTER_PIMEM			4
149*4882a593Smuzhiyun #define MASTER_GIC			5
150*4882a593Smuzhiyun #define SLAVE_APPSS			6
151*4882a593Smuzhiyun #define SNOC_CNOC_SLV			7
152*4882a593Smuzhiyun #define SLAVE_SNOC_GEM_NOC_GC		8
153*4882a593Smuzhiyun #define SLAVE_SNOC_GEM_NOC_SF		9
154*4882a593Smuzhiyun #define SLAVE_OCIMEM			10
155*4882a593Smuzhiyun #define SLAVE_PIMEM			11
156*4882a593Smuzhiyun #define SLAVE_SERVICE_SNOC		12
157*4882a593Smuzhiyun #define SLAVE_PCIE_0			13
158*4882a593Smuzhiyun #define SLAVE_PCIE_1			14
159*4882a593Smuzhiyun #define SLAVE_QDSS_STM			15
160*4882a593Smuzhiyun #define SLAVE_TCU			16
161*4882a593Smuzhiyun 
162*4882a593Smuzhiyun #endif
163