1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Interconnect framework driver for i.MX SoC 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (c) 2019-2020, NXP 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #ifndef __DT_BINDINGS_INTERCONNECT_IMX8MQ_H 9*4882a593Smuzhiyun #define __DT_BINDINGS_INTERCONNECT_IMX8MQ_H 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #define IMX8MQ_ICN_NOC 1 12*4882a593Smuzhiyun #define IMX8MQ_ICS_DRAM 2 13*4882a593Smuzhiyun #define IMX8MQ_ICS_OCRAM 3 14*4882a593Smuzhiyun #define IMX8MQ_ICM_A53 4 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun #define IMX8MQ_ICM_VPU 5 17*4882a593Smuzhiyun #define IMX8MQ_ICN_VIDEO 6 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun #define IMX8MQ_ICM_GPU 7 20*4882a593Smuzhiyun #define IMX8MQ_ICN_GPU 8 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun #define IMX8MQ_ICM_DCSS 9 23*4882a593Smuzhiyun #define IMX8MQ_ICN_DCSS 10 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun #define IMX8MQ_ICM_USB1 11 26*4882a593Smuzhiyun #define IMX8MQ_ICM_USB2 12 27*4882a593Smuzhiyun #define IMX8MQ_ICN_USB 13 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun #define IMX8MQ_ICM_CSI1 14 30*4882a593Smuzhiyun #define IMX8MQ_ICM_CSI2 15 31*4882a593Smuzhiyun #define IMX8MQ_ICM_LCDIF 16 32*4882a593Smuzhiyun #define IMX8MQ_ICN_DISPLAY 17 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun #define IMX8MQ_ICM_SDMA2 18 35*4882a593Smuzhiyun #define IMX8MQ_ICN_AUDIO 19 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun #define IMX8MQ_ICN_ENET 20 38*4882a593Smuzhiyun #define IMX8MQ_ICM_ENET 21 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun #define IMX8MQ_ICM_SDMA1 22 41*4882a593Smuzhiyun #define IMX8MQ_ICM_NAND 23 42*4882a593Smuzhiyun #define IMX8MQ_ICM_USDHC1 24 43*4882a593Smuzhiyun #define IMX8MQ_ICM_USDHC2 25 44*4882a593Smuzhiyun #define IMX8MQ_ICM_PCIE1 26 45*4882a593Smuzhiyun #define IMX8MQ_ICM_PCIE2 27 46*4882a593Smuzhiyun #define IMX8MQ_ICN_MAIN 28 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun #endif /* __DT_BINDINGS_INTERCONNECT_IMX8MQ_H */ 49